This study compared two hypothetical transit scenarios with the current bus transit system for serving the transit passengers of Ann Arbor, Michigan, for a typical fall weekday in 2013. One scenario consists of an automated taxi system that allows only one rider at a time, and the other consists of a similar automated taxi system that allows ridesharing for up to four passengers. The two automa...

The harmonic in distribution systems becomes an important problem due to an increase in nonlinear loads. This paper presents a new approach based on a graph algorithm for optimum placement of passive harmonic filters in a multi-bus system, which suffers from harmonic current sources. The objective of this paper is to minimize the network loss, the cost of the filter and the total harmonic disto...

Previous studies have suggested a relationship between bile duct stones and periampullary duodenal diverticula. The aim of the present study was to examine this association in more detail, including step-wise logistic regression to identify independent predictors for the presence of diverticula. Clinical, endoscopic and radiological data were analysed from 794 consecutive subjects with bile duc...

Trambadia: In the past few years we have used HLS tools for designing SoCs and different types of IP blocks. These include AMBA [Advanced Microcontroller Bus Architecture] bus IP blocks like AXI [Advanced eXtensible Interface], AHB [Advanced High-performance Bus], APB [Advanced Peripheral Bus], AHB-Multilayer, and AMBA cross-bus bridges for AXI, AHB, and APB. Similarly, HLS tools have also been...

Amajor concern with high-performance general-purpose workstations is to speed up the execution of commands, uniprocess applications, and multiprocess applications with coarseto medium-grain parallelism. To that end, a simple extension of a uniprocessor machine such as a shared-bus, shared-memory architecture can be employed.1 Both kinds of machines generally use the same operating-system model ...

In this paper, we study the performance of multiple bus networks with full bus-memory connection, single bus-memory connection, and partial bus-memory connection. Besides, we also propose one type of multiple bus networks, called partial bus networks with K classes. Under a nonuniform requesting model, hierarchical requesting model, the performance of the above multiple bus networks is anal zed...

Abstract -This paper describes the implementation of an external L3 Cache memory bus used in ItaniumTM processor. The cache bus has been designed for adequate bandwidth required in high-end servers, and provides data to the processor at the processor core frequency. High-speed I/O circuits used to accomplish this state-of-the-art bus design are discussed in detail. The center-tapped-termination...