Use of a standard non-rad-hard digital cell library in the rad-hard design can be cost-effective solution for space applications. In this paper we demonstrate how flip-flop, as one most vulnerable cells, converted into flip-flop without modifying its internal structure. We present five variants Triple Modular Redundancy (TMR) flip-flop: baseline TMR latch-based True-Single Phase Clock (TSPC) sc...

We demonstrate that 80 Gb/s data-packets can be all-optically switched into two different ports employing an optical wavelength converter controlled by a monolithically integrated optical flip-flop memory. The optical wavelength converter consists of a semiconductor optical amplifier and an optical filter. The integrated optical flip-flop exhibits single-mode operation, has 35 dB contrast ratio...

A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leak current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of th...

This article presents a research work on the design and synthesis of sequential circuits and flip-flops that are available in digital arena; and describes a new synthesis design of reversible counter that is optimized in terms of quantum cost, delay and garbage outputs compared to the existing designs. We proposed a new model of reversible T flip-flop in designing reversible counter. Keywords—F...

Glycerophospholipid flip-flop across biogenic membranes such as the endoplasmic reticulum (ER) is a fundamental feature of membrane biogenesis. Flip-flop requires the activity of specific membrane proteins called flippases. These proteins have yet to be identified in biogenic membranes and the molecular basis of their action is unknown. It is generally believed that flippase-facilitated glycero...

A low power pulse triggered flip-flop with signal feed through scheme using Conditional Pulse Enhancement technique is presented in this paper. The proposed design adopts a modified True Single Phase Clock Latch structure and employs a signal feed through scheme to enhance the delay. The long discharging path problem in conventional explicit type pulse triggered flip flops are successfully solv...

The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance CMOS circuits. Understanding the suitability of flipflops and selecting the best topology for a given application is an important issueto fulfill the need of the design to satisfy low power and high performance circuit. This paper presents a wides...

We demonstrate all-optical switching of 80 Gb/s data-packets using an optical wavelength converter that consists of an SOA and an optical filter. The wavelength converter is controlled by a monolithically integrated optical flip-flop memory. Introduction High-speed all-optical switches offer advantages in power consumption, foot-print and switching architectures compared to their electronic cou...

In this paper, we have modelled the flip-flop clock to output delay dependency on the data arrival time and introduced this phenomenon in timing analysis. Traditionally, finding the minimum clock period of a flip-flop based sequential design was based on the assumption that the setup-time and clock to output delay of a flip-flop are constant and hence each stage of the pipeline can be analyzed ...

This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops. Based on the simulation result...