An Adder is one of the significant hardware blocks in most digital systems such as digital signal processors and microprocessors etc. Over the last few decades lot of research have been carried out in order to design an efficient adder circuits in terms of compactness, high speed and low power consumption. However, area and speed are two conflict parameters. So, improving speed results always i...

In this paper we show how case-based reasoning techniques can be used to extract and reuse solutions previously found by a heuristic (a genetic algorithm in our case) used to solve problems in a specific domain (MSI and SSI combinational circuit design). This reuse of partially built solutions allows us to improve convergence time of our heuristic since the building blocks of the “good" solutio...

A series of complex logic gates were constructed based on graphene oxide and DNA-templated silver nanoclusters to perform both arithmetic and nonarithmetic functions. For the purpose of satisfying the requirements of progressive computational complexity and cost-effectiveness, a label-free and universal platform was developed by integration of various functions, including half adder, half subtr...

Abstract This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder (M2CSA) using single leaf cell i.e., 2–1 Multiplexer. M2CSA is designed new type Excess-1 block. The block in distinct way multiplexers. architectures the proposed carry select adder and its internal blocks are completely when compared to existing adders. 4-, 8-, 16-, 32-, 64-bit M2CSAs use multiplexer ...

In this paper, we assimilate and integrate two recent developments in prefix adder design and theory to create a fault-tolerant, real-time reconfigurable prefix adder. By exploiting the inherent redundancy of a Kogge-Stone adder we are able to extract signals to detect and correct from a single-fault. Our 16-bit design consumes less than 44% the hardware overhead of a comparable triple modular ...

This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-ofproducts expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EXSOPs where some outputs of the function are minimized in the compl...

This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indic...

1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic gate in extrinsic EHW allows us to describe behaviour of any multi-input multi-output logic function. The circuit is represented in the form of connections and functionalities of a rectangular array of building block...

This paper presents anthraquinone and benzimidazole based hybrid molecular architect as the state of the art for multifunctional molecular logic circuits. The moleculator exhibits differential output behavior towards F(-), Zn(2+) and Cu(2+) ions to provide opportunities for elaboration of XOR, INHIBIT, XNOR, AND, OR, NOR, logic functions and their integrated logic functions half-adder, half-sub...