In this paper, a new method of patient monitoring system has been proposed by employing a system on programmable chip (SOPC) using field programmable gate array (FPGA) processor, due to drawbacks in embedded based patient monitoring system. SOPC based FPGA system measures multiple bio-signals such as Electrocardiogram (ECG), saturation level of oxygen (SaO2) in hemoglobin, body temperature and ...

In this paper, an optimized programmable demodulation scheme suitable for M-PSK/16QAM signals is proposed. The scheme adopts the conception of component reuse by exploring the demodulation structures of M-PSK and 16QAM respectively. The carrier phase recovery circuit uses the reduced complexity Costas loop. The symbol timing synchronization circuit adopts Gardner loop with offset cancellation. ...

In this paper, a description of a general purpose neural network chip with on-chip learning is given. The design is implemented using Xilinx Vertex II XCV 1000 Field Programmable Gate Array (FPGA). An XOR gate simulation was used as a testing application. Results and comparison of both software and hardware implementations are listed. A second testing application in noise cancellation and voice...

This work reports a non-pipelined AES (Advanced Encrypted Standard) FPGA (Field Programmable Gate Array) architecture, with low resource requirements. The architecture is designed to work on CBC (Cipher Block Chaining) mode and achieves a throughput of 1.45 Gbps. This implementation is a module of a configuration library for a Cryptographic Reconfigurable Platform (CRP).

We describe the architecture and algorithm development for a field programmable gate array (FPGA) wideband telemetry receiver prototype capable of processing data rates in excess of 100 megabits per second (Mbps). The high-speed parallel implementations of the matched filter, carrier phase tracking loop, and symbol timing recovery loop are discussed, along with simulation and hardware performan...

In this paper a PID controller is designed and it’s implemented on Field Programmable Gate Array (FPGA) by two method: in first method PID controller is designed in time domain and in second method PID is designed in frequency domain (Z domain) and final two method compare together. The filter that designed in time domain is more accurate than other method.

⎯ This paper presents a model-based Register Transfer Level (RTL) design of a 4x2 Multiple-Inputs Multiple-Outputs (MIMO)-Orthogonal Frequency Domain Multiplexing (OFDM) wireless communication systems transmitter and its Field Programmable Gate Array (FPGA) implementation. This system provides a maximum of 600 Mbps with 20 meter of propagation distance using 80 MHz baseband bandwidth with 4x2 M...

In this paper, we present a new contribution of FPGAs (Field-Programmable Gate Array) for control of electrical machines. A detailed description of the structure of direct torque control for PMSM drive, a bench test was realized by a prototyping platform, the experimental results obtained show the effectiveness and the benefit of our contribution and the different steps of implementation for th...

This paper presents an image processing system based on smart camera platform, whose two principle elements are a Pan-Tilt-Zoom (PTZ) camera and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the PTZ Camera. With the advent of today's highly integrated Field Progr...

Reconfigurable coprocessors, most commonly implemented with field programmable gate array (FPGA) technology, have been shown effective in accelerating certain classes of applications. Computation-intense kernels can be selected automatically or by hand for acceleration using the coprocessor. For each kernel selected, aconfiguration must be constructed to implement the computation graph of the k...