This paper presents a systematic design for yield enhancement of asynchronous logic circuits using 3-D (3Dimensional) integration technology. In this design, the target asynchronous circuits on one planar device layer which is fabricated with aggressive technology, are built on fault tolerant graph models with extra spare resources, and can be reconfigured by autonomous reconfiguration logic on...

We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this a...

As transistors become increasingly smaller and faster and noise margins become tighter, circuits and chip specially microprocessors tend to become more vulnerable to permanent and transient hardware faults. Most microprocessor designers focus on protecting memory elements among other parts of microprocessors against hardware faults through adding redundant error-correcting bits such as parity b...

The growing number of circuits implemented in Field Programmable Gate Arrays (FPGAs) and the increased susceptibility, due to higher integration levels, of these devices to soft faults caused by radiation at ground level is leading the scientific and technical community to the study of new fault tolerant designs and solutions, and how they can be verified and validated. Using fault injection te...

One of the most significant challenges facing the development of linear optics quantum computing (LOQC) is mode-mismatch, whereby photon distinguishability is introduced within circuits, undermining quantum interference effects. We examine the effects of mode-mismatch on the parity (or fusion) gate, the fundamental building block in several recent LOQC schemes. We derive simple error models for...

The field of digital electronics has since its start been in constant progression. Integrated circuits are becoming more and more dense as there is a demand for more speed and functionality. A fundamental requirement which is increasingly hard to satisfy with this development is that the system does not fail. Fault tolerance and managing noise are both major long term challenges of the digital ...

This paper focuses on the investigation of efficient methods to evaluate circuit fault-tolerance. We propose a fault-tolerance evaluation method based on the Belief Propagation (BP) algorithm. Compared with existing approaches, our algorithm is more efficient in terms of memory requirements and CPU time. The algorithm can easily run on multiple CPUs to achieve parallel processing, and thus furt...

In this paper, several fault-tolerant hardware implementations of Systolic Arrays on reconfigurable devices, such as FPGAs, are investigated and primal selection criteria such as resource utilization, computation time, advantages and disadvantages of every fault-tolerant method are presented. Since the main goal of the designs presented herein is the high performance of the implementations, the...

Accommodating billions of transistors on a single die, VLSI technology has reached a scale where principal physical limitations have a strong impact on design principles. Among the particular challenges are maintaining the synchronous clock abstraction in settings where wiring delays dominate over switching delays, and coping with increasing transient failure rates. In an attempt to address som...

The application of current generation computing machines in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for reviewing the worst-case error behavior of computing devices for fault-tolerant computation. In this work, we propose an exact probabilistic error model that can compute the maximum error over all possible input spac...