|Gate-sizing is an eeective technique to optimize CMOS circuits for dynamic power dissipation and performance while dual-V th (threshold voltage) CMOS is ideal for leakage power reduction in low voltage circuits. This paper focuses on simultaneous dual-V th assignment and gate-sizing to minimize the total power dissipation while maintaining high performance. An accurate power dissipation model ...

Gate-sizing is an effective technique to optimize CMOS circuits for dynamic power dissipation and performance while dual-V,h (threshold voltage) CMOS is ideal for leakage power reduction in low voltage circuits. This paper focuses on simultaneous dual-V,h assignment and gate-sizing t o minimize the total power dissipation while maintaining high performance. An accurate power dissipation model t...

This paper presents a combined fault detection and discrimination strategy for CMOS logic incorporating active resource mitigation and monitoring. The approach is demonstrated for a NOR gate using a dual redundant gate design with selective mitigation and analogue or digital detection. The potential benefits of the approach are discussed with respect to resource awareness and management within ...

Variable rate application of fertilisers with traditional spinner-type spreaders is known to suffer from spread pattern uniformity variability as a function of application rate. To demonstrate this variability, simulations using models from the literature were carried out for two cases: (1) a dual disc spreader with segment-type feed gates; and (2) a single disc spreader with conical feed gates...

In this paper we investigate the electrical characteristics of a new structure of gate all around strained silicon nanowire field effect transistors (FETs) with dual dielectrics by changing the radius (RSiGe) of silicon-germanium (SiGe) wire and gate dielectric. Indeed the effect of high-κ dielectric on Field Induced Barrier Lowering (FIBL) has been studied. Due to the higher electron mobility ...

A new dual-Vt static CMOS circuits, the Split-Gate dual-Vt (SGDVT) logic. are devised. Their performance is compared to that of all-low-Vt. all-high-Vt. and other dual-Vt circuits in terms of speed and energy consumption (both static and dynamic). They achieved speeds close to that of the all-low-Vt circuits. lower leakage (both stand-by and active) than other dual-Vt circuits. and lower leakag...

The effect of nitrogen (N14) implant into dual-doped polysilicon gates was investigated. The electrical characteristics of sub-0.25m dual-gate transistors (both pand n-channel), MOS capacitor quasi-static C V curve, SIMS profile, poly-Si gate Rs, and oxide Qbd were compared at different nitrogen dose levels. A nitrogen dose of 5 10 cm 2 is the optimum choice at an implant energy of 40 KeV in te...

This paper describes a parallel single-rail self-timed adder using dual gate MOSFETs which builds on a recursive formulation for performing multibit binary addition. Thus the addition is equivalent for those bits that do not need any carry chain propagation and the circuit attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. ...