An improved process for graphene transfer was used to demonstrate high performance graphene enabled vertical organic field effect transistors (G-VFETs). The process reduces disorder and eliminates the polymeric residue that typically plagues transferred films. The method also allows for purposely creating pores in the graphene of a controlled areal density. Transconductance observed in G-VFETs ...

In this paper, we have investigated the effect of a single Grain Boundary (GB) on the performance of decananometer-scale Thin Film Transistors (TFTs) by using the calibrated energy balance transport model and a continuous trap state distribution at the GB. We have found that the GB potential barrier suppresses the subthreshold slope and leakage current in devices, where the DIBL effect and punc...

III-V-on-nothing (III-VON) metal-oxide-semiconductor field-effect transistors (MOSFETs) are experimentally demonstrated with In0.53Ga0.47As as channel and atomic layer deposited Al2O3 as gate dielectric. A hydrochloric acid based release process has been developed to create an air gap beneath the InGaAs channel layer, forming the nanowire channel with width down to 40 nm. III-VON MOSFETs with c...

This paper presents charge-based continuous equations for the transconductance and output conductance of submicrometer Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFET. The effects of carrier velocity saturation, channel length modulation and drain-induced barrier lowering were taken into account in the proposed equations. Experimental results were used to test the validity of the equatio...

Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier l...

A new method of forming low-resistance, ultra-shallow p+ junctions for improved PMOSFET short-channel performance is presented. Ultra-shallow Sio,8Geo,2/Si heterojunctions self-aligned to the gate electrode are formed by Ge ion implantation. Afterwards, sidewall spacers are formed and a deep B implant is performed to form the deep source/drain (S/D) contact regions. Upon post-implant annealing,...

A double gate FinFET can reduce drain induced barrier lowering and improve threshold (short channel effects). In this paper, a very important geometrical parameter, that is, the fin width of a FinFET has been analyzed. In this article, a double gate n channel FinFET with a gate length of 20nm has been reported. The transfer characteristics of the FinFET at various fin widths have been obtained ...

In this work, sub-micron-thick AlN/GaN transistors (HEMTs) grown on a silicon substrate for high-frequency power applications are reported. Using molecular beam epitaxy, an innovative ultrathin step-graded buffer with total stack thickness of 450 nm enables one to combine excellent electron confinement, as reflected by the low drain-induced barrier lowering, leakage current below 10 µA/mm and t...