This paper analyzes the sources of jitter in a DLL and presents a behavioral model for fast DLL optimization. An algorithm to simulate the DLL in open loop is demonstrated. This procedure, together with the behavioral modeling, greatly reduces the simulation time of DLL when compared to the closeloop DLL simulation. In order to optimize the DLL performance, the dependence of the output jitter v...

This thesis presents a 3.6-GHz, 500-kHz bandwidth digital AE frequency synthesizer architecture that leverages a recently invented noise-shaping time-to-digital converter (TDC) and an all-digital quantization noise cancellation technique to achieve excellent in-band and out-of-band phase noise, respectively. In addition, a passive digital-toanalog converter (DAC) structure is proposed as an eff...

This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2 ) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8m CMOS technology is des...

A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90◦ phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3◦ at 400MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with power-down mode. The proposed DCPS provides...

Multipath propagation is a major source of degradation in the performance of conventional PN code tracking loops. The mean-square tracking error of a conventional delay-locked loop (DLL) exhibits an irreducible floor due to the presence of closely spaced multipath components. In this paper, we present a new PN code tracking algorithm that does not suffer from the presence of multipath component...

2 Digitizer 1GHz clock generation and control 5 2.1 Digitizer clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Reference generation and coarse clock delay control . . . . . . . . . . . . . . . . . . . 6 2.3 Phase locked-loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Digitizer clock fine delay control . . . . . . . . ...

In this paper, a new direction of arrival (DOA) estimation algorithm, direction lock loop (DiLL), is proposed. It has a similar concept to the delay lock loop (DLL) that is used for synchronization. It estimates the DOA of a signal by iterations, and can track the DOA of a moving source. The DiLL scheme is found to track better than the DOA estimation scheme based on the PASTd, and its performa...

This paper examines the problems of symbol timing estimation and timing recovery for ultra wideband impulse radio signals. Two different approaches based on the maximum likelihood technique are investigated. The first approach is based on derivative matched filter and the second one takes advantage of the early-late technique. Furthermore, two non-coherent timing recovery circuits are proposed ...

The proposed architecture is an all-digital delayand phase-locked loops circuit, which has several advantages, namely, it does not have the jitter accumulation issue that is normally encountered in analog DLL/PLL and can be adapted easily for different FPGA families as well as implemented as an integrated circuit ability of DLLs and PLLs to provide fixed timing relationships lets component manu...