 SEMATECH, a US based consortium of ten major semiconductor manufacturers, is developing a comprehensive system for the design of ICs below .25 μm, which exploits hierarchy, constraint directives, incremental processing, and concurrent design and analysis. This development of SEMATECH's Chip Hierarchical Design System (CHDS) includes major technological investments in algorithms for design pla...

The basic \quadratic placement" methodology is rooted in works by Wipper et al. 36], Cheng and Kuh 8], Tsay et al. 32, 33, 34] and many others. It is also, reputedly, an approach that has been used in commercial and in-house tools for placement of standard-cell and gate-array designs. The quadratic placement methodology entails (i) solving recursively generated sparse systems of linear equation...

The evolution of Integrated Circuit designing has been a real game changer in the field of VLSI system in the past quarter century. Very deep sub-micron (VDSM) technologies embracing sub-100nm wafer design technologies, to take advantage of the superior integration possibilities. At these technologies, many phenomena affect gate, path delay or wire delays. Now a days, crosstalk noise or crossta...

In integrated circuits accurate runtime sensing of on-chip temperature is required to establish efficient dynamic thermal management techniques. In this paper, we propose novel sensor allocation and placement algorithm and thermal sensing technique for indirect temperature estimation at arbitrary locations. As the experimental results indicate, the runtime thermal estimation method reduces temp...

As technology scales down, coupling between nodes of the circuits increases and becomes an important factor in interconnection analysis. In many cases like the deep submicron technology (DSM), the coupling between lines (inter-wire capacitance) is strong and the power consumed by parasitic capacitance is non-negligible [1-6]. In this work, we employ the differential low-weight encoding [1] to r...

In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeaters insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeaters insertion. VIJIM algorithm has been implemented to design a robust inverter...

Scaling in the deep submicron (DSM) regime has fundamentally altered the primary issues affecting VLSI design. The emergence of DSM-related problems has resulted in a proliferation of design techniques that attempt to alleviate these newer effects in current flows. However, future design methodologies would be required to undergo a paradigm shift to comprehensively address these problems. A few...

Day by Day as the technology is shrinking and as chip density and frequency are increasing, power dissipation on data bus has become the most predominant factor than the power dissipation in other part of the circuitry. Further de facto, the inter-wire capacitance becomes a dominating factor in proliferating Deep Submicron Technology (DSM) compared to substrate capacitance. So, the earlier sche...

Due to the expected increase of defects in circuits based on deep submicron technologies, reliability has become an important design criterion. Although different approaches have been developed to estimate reliability in digital circuits and some measuring concepts have been separately presented to reveal the quality of analog circuit reliability in the literature, there is a gap to estimate re...

The optimization of a digital system in deep submicron technology should be done with two basic principles: energy waste reduction and energy-delay tradeoff. Increased energy resources obtained through energy waste reduction are utilized through energy-delay tradeoffs. The previous practice of obliviously pursuing performance has led to the rapid increase in energy consumption. While energy was...