Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology and its applications to accurately and efficiently predict power and temperatu...

As MOSFETs are scaled into the deep sub-micron (decanano) regime, quantum mechanical confinement and tunnelling start to dramatically affect their characteristics. It has already been demonstrated that the density gradient approach can be successfully calibrated in respect of vertical quantum confinement at the Si/SiO2 interface and can reproduce accurately the quantum mechanical threshold volt...

Transient current testing (IDDT) has been often cited as an alternative and/or supplement to IDDQ testing. In this article we investigate the potential of transient current testing in faulty chip detection with silicon devices. The effectiveness of the IDDT test method is compared with I D D e as well as with SA-based voltage testing. Photon emission microscopy is used to localize defects in se...

This paper argues that the existing approaches to modeling and characterization of IC malfunctions are inadequate for test and yield learning of Deep Sub-Micron (DSM) products. Traditional notions of a spot defect and local and global process variations are analyzed and their shortcomings are exposed. A detailed taxonomy of process-induced deformations of DSM IC structures, enabling modeling an...

Very Deep Sub-Micron (VDSM) defects are resolved as Statistical Post-ProcessingTM (SPP) outliers of a new IDDQ screen. The screen applies an IDDQ pattern once to the Device Under Test (DUT) and takes two quiescent current measurements. The quiescent current measurements are taken at nominal and at subthreshold supply voltages. The screen is demonstrated with 0.18μm and 0.13μm volume data. The s...

The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. After recent improvement techniques on PLA, PLA becomes more attractive for designers especially in GHz technology with deep sub-micron sizing. In this paper we will try to introduce the cross-talk problem solution in DSM, in PLA Network and also try to give the usage of PLA in GHz technology and the ad...

minimum energy per bit required for communicating through deep sub-micron buses at a given bit rate is solved with an explicit answer. It is also shown that this minimum energy per bit can be achieved using coding techniques. Moreover, a differential coding scheme is proposed that achieves most of the possible energy reduction. The methodology given here also applies to more general communicati...

The performance of CMOS image sensors in a deep sub-micron CMOS process is limited by two factors: 1) The increasing pixel temporal noise floor dominated by the 1/f noise from the pixel source follower (SF) and 2) The decreasing pixel analog swing due to the supply voltage scaling. In this paper, we present the possibility of using a buried channel n-MOST as the in-pixel source follower to redu...

This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and Electro Static Discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5V/um Human Body Model (HBM) were demonstrated. Significant silicon area reduction was demonstrated in deep-sub micron...