نتایج جستجو برای: custom instruction
تعداد نتایج: 62212 فیلتر نتایج به سال:
Power consumption of multimedia applications executing on embedded cores is heavily dependent on data transfers between system memory and processing units. In this paper, a power optimizing methodology based on data-reuse decisions and the development of a custom memory hierarchy is extended in order to determine the optimal solution in a rapid and reliable way. Data-reuse transformations are a...
Three generations of Alpha microprocessors have been designed using a proven custom design methodology. The performance of these microprocessors was optimized by focusing on high-frequency design. The Alpha instruction set architecture facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths. Digital has developed six generations of...
The system on chip paradigm consists of one or more instruction set processors integrated with custom hardware on a single integrated circuit. A uni-processor real-time kernel is presented that integrates hardware coprocessors by viewing them as system resources to be scheduled in conjunction with the processor. The kernel implements the earliest-deadline first scheduling policy. To demonstrate...
The use of FPGA based custom computing platforms is proposed for implementing linearly structured Genetic Programs. Such a context enables consideration of micro architectural and instruction design issues not normally possible when using classical Von Neumann machines. More importantly, the desirability of minimising memory management overheads results in the imposition of additional constrain...
In this paper we present the Molen programming paradigm, which is a sequential consistency paradigm for programming Custom Computing Machines (CCM). The programming paradigm allows for modularity and provides mechanisms for explicit parallel execution. Furthermore it requires only few instructions to be added in an architectural instruction set while allowing an almost arbitrary number of op-co...
A 300-MHz, custom 64-bit VLSI, second-generation Alpha CPU chip has been developed. The chip was designed in a 0.5-um CMOS technology using four levels of metal. The die size is 16.5 mm by 18.1 mm, contains 9.3 million transistors, operates at 3.3 V, and supports 3.3-V/5.0-V interfaces. Power dissipation is 50 W. It contains an 8-KB instruction cache; an 8-KB data cache; and a 96-KB unified sec...
This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to improve fault tolerance in microprocessors. Our takes advantage modern multicore processor resources combine software-based with custom hardware observer. The first is used duplicate data and instruction flows; meanwhile, second charge control-flow monitoring. proposal has been implemented ARM microprocessor ...
In this paper, we present techniques for mitigating the Negative Bias Temperature Instability (NBTI) effect on extensible processors. Firstly, the effect of NBTI on the extended instruction set architecture and the arithmetic logic unit of extensible processors is studied. The study includes modeling the circuit delay increase due to the NBTI and analyzing its impact on the processor lifetime. ...
This study focuses on accelerating the optimization of motion estimation algorithms, which are widely used in video coding standards, by using both the paradigm based on Altera Custom Instructions as well as the efficient combination of SDRAM and On-Chip memory of Nios II processor. Firstly, a complete code profiling is carried out before the optimization in order to detect time leaking affecti...
Many guest languages are implemented using the Java Virtual Machine as a host environment. There are two major implementation choices: custom compilers and so-called hosted interpreters. Custom compilers are complex to build but offer good performance. Hosted interpreters are comparatively simpler to implement but until now have suffered from poor performance. We studied the performance of host...
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