Despite intensive research on distributed processor interconnection architectures, relatively little work has been done on the performance analysis of such systems. The reason for this, besides the complexity of the behavior of such systems, is that Queueing Theory cannot easily handle systems consisting of many tightly interacting components. An alternate approach, based upon statistical mecha...

Recent research in nanoscale computing offers multiple techniques for producing large numbers of parallel nanowires (NWs). These wires can be assembled into crossbars, two orthogonal sets of parallel NWs separated by a layer of molecular devices. In a crossbar, pairs of orthogonal NWs provides control over the molecules at their crosspoints. Hysteretic molecules act as programmable diodes, allo...

We would like to thank Adisak Mekkittikul for help and numerous discussions about the scheduler design, particularly with the pipelining technique described on page 2. 11 References [1] http://tiny-tera.stanford.edu/tiny-tera [2] N.McKeown, " Scheduling Cells in an input-queued switch, " PhD Thesis,

In this paper we investigate the unique potential of optics to provide a family of arbitration free topologies that are not realizable using conventional electronics. This is accomplished by creating a directly connected fabric of waveguides that can be configured to support everything from a crossbar to fully connected topologies. The large number of waveguides required to create a Directly Co...

The memristor is promising to be the basic cell of next-generation computation systems. Compared to the traditional MOSFET device, the memristor is efficient over energy and area. But one of the biggest challenges faced with researchers is how to program a memristor’s resistance precisely. Recently, an algorithm designed to save 8 valid bits in each memristor is proposed, but this is still not ...

In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of clustering adopted in processors is to replace the centralized instruction scheduler with multiple smaller schedulers that work in parallel within a single chip. Studies have found that existing interconnects connecting ...

New reconfigurable computing crossbar architecture based on memFETs has been developed and patented. This breakthrough technology, developed by a group of scientist from UAB and UPC represents an alternative to conventional computational systems as it adapts the size and composition dynamically, without any changes in CMOS manufacturing process required. Partners to further develop the system a...

Since Clos gave the first construction of a strictly nonblocking multistage interconnection network, only a few other constructions have been proposed in almost a half-century. In this paper, we introduce a constructive class of networks which utilizes crossbars of virtually any size and for which the sizes can vary from stage to stage. The interconnection between stages is a generalized shuffl...

A sparse crossbar (n,m, c)-concentrator is a bipartite graph with n inputs and m outputs in which any c or fewer inputs can be matched with an equal number of outputs, where c is called its capacity. Sparse crossbar concentrators play a key role in multiplexing signals in communication systems and constructing permutation and generalized connection networks. In this paper we present a number of...

Interconnection networks consist of a set of switches interconnected by point-to-point links, and hosts linked to those switches through a network interface card. These networks are becoming increasingly popular as a cost-effective alternative to parallel computers. One of the most wellknown example is the Myrinet network. These networks use techniques and incorporate components that have been ...