We proposed a neural segmentation model that is suitable for implementation in analog VLSIs using conventional CMOS technology. The model consists of neural oscillators mutually couple through synaptic connections. The model performs segmentation in temporal domain, which is equivalent to segmentation according to the spike timing difference of each neuron. Thus, the learning is governed by sym...

A low-power analog sensor front-end is described that reduces the energy required to extract environmental sensing spectral features without using Fast Fouriér Transform (FFT) or wavelet transforms. An Analog Harmonic Transform (AHT) allows selection of only the features needed by the back-end, in contrast to the FFT, where all coefficients must be calculated simultaneously. We also show that t...

A CMOS image sensor with an integrated wire grid polarizer to sense the polarization of light is presented. The chip consists of an array of 128 by 128 pixels, and it has been designed and fabricated in a CMOS 180nm process. The sensed polarization information is represented and analyzed in both the analog and the digital domain. Extinction ratios of 6.3 and 7.7 were achieved in analog represen...

An analog circuit for edge detection was proposed based on vertebrate outer retinas. The chip which contained 40× 40 unit circuits in a two-dimensional array was fabricated with 0.35 μm CMOS process. Edge images were experimentally observed in a brightness range over 3 orders of magnitude. It was clarified by simulation with the simulation program with integrated circuit emphasis (SPICE) that a...

A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a bulk CMOS chip, the core circuit blocks are always latchup sensitive due to a low holding voltage of the parasitic SCR path. The proposed latchup prevention methodology and circuit design can detect and stop the occurr...

A neurocomputer based on a high-density analog integrated circuit developed in a 3 mum CMOS technology has been built. The 1.6 mmx2.4 mm chip contains 18 neurons and 161 synapses in three layers, and provides 16 inputs and 4 outputs. The weights are stored on storage capacitors of the synapses. A formalization of the error back-propagation algorithm which allows the use of very small nonlinear ...

This paper presents an analog VLSL circuit for implementation of Artificial Neural Networks (ANNs ). The building blocks of the proposed circuit include Differential voltage current controlled source (DVCCS), Super MOSFET and Differential voltage controlled voltage source (DVCVS) which are used to multiply incoming analog signals with variable weights, and current in / current out sigmoid funct...

Manuscript received June 16, 1999. Manuscript revised August 14, 1999. † The authors are with the Department of Electrical Engineering, Science University of Tokyo, Noda-shi, 278-8510 Japan. SUMMARY A lower impedance terminal is necessary for an input terminal of current-mode circuits and an output terminal of voltage-mode circuits to reduce an error and distortion in analog signal processing. ...

Abstmcf A CMOS neural network integrated circuit is discussed, which was designed for very high speed applications. This full-custom, mixed analog-digital chip implements a fully connected feedforward neural network with 70 inputs, 6 hidden layer neurons and one output neuron. The neurons perform inner product operation and have sigmoid-like activation function. The 70 network inputs and the ne...