The manufacturability benefits of restricted design style have long been recognized in the implementation of SRAM and FPGA circuits. However, the ASIC community has shied away from layout restrictions for the fear of stifling designers’ creativity and creating an inefficient area, and thus cost, product. Nevertheless, as the design features required began to approach nanometer-scale dimensions,...

Defect rate in Nanoelectronics is much higher than conventional CMOS circuits. Hardware redundancy can be a suitable solution for fault tolerance in nano level. A voter circuit is a part of a redundancy based fault tolerant system that enables a system to continue operating properly in the event of one or more faults within its components. Robustness of the voter circuit defines the reliability...

This paper presents a new methodology together with its corresponding software analysis that create incentives for quantum circuit synthesis. Our circuit synthesis and architecture design approaches bring a new view on quantum circuit synthesis. This paper presents a software architecture that transforms a high-level software circuit description into a circuit layout, thus attaining quantum cir...

Title of Thesis: SECURITY THROUGH OBSCURITY: LAYOUT OBFUSCATION OF DIGITAL INTEGRATED CIRCUITS USING DON’T CARE CONDITIONS Sana Mehmood Awan, Master of Science, 2015 Directed By: Professor Gang Qu, Department of Electrical and Computer Engineering and Institute for Systems Research, University of Maryland Contemporary integrated circuits are designed and manufactured in a globalized environment...

Due to substantial mixed analog-digital circuit integration in one chips CMOS digital imager cannot be considered only as a photoelectric transducer. In this paper, we have identzjied timing and circuit layout considerations that are critical for implementing a digital CMOS camera-on-a-chip. An optimized binaryscaled tree-topology power routing has been shown to be critical for minimizing chip ...

In this paper a dual voltage CMOS low power output pad is presented. The pads are the interface circuits between the core and the package pins of any integrated circuit. The power consumption of these pads it is a very important parameter for the global power consumption of the integrated circuit that includes them. The proposed pad includes a pre-driver and a final output stage including ESD(e...

The limiting factor for high-performance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extremely important and timely research area, we analyze in this paper the ci...

Improved layout of QCA(quantum-dot cellular automata)based PLA (programmable logic array) that enhance the defect tolerance is proposed, in order to develop next generation circuit technology that replace the conventional CMOS technology. We analyze which QCA device (quantum-dot cell) limits the defect tolerance of the AND/OR plane cell of the QCA-PLA by using QCA circuit simulator or QCADesign...

Layout stitching is a repetitive and tedious task of the radio frequency integrated circuit (RFIC) design process. While academic research on layout splicing algorithms mainly focuses analog digital circuits, there still lack well-developed for RFICs. An RFIC system usually has symmetrical layout, such as transmitter receiver components, low-noise amplifier (LNA), an SPDT switch, etc. This pape...

This paper applies to the scientific area of electronic design automation (EDA) and addresses the automatic sizing of analog integrated circuits (ICs). Particularly, this work presents an innovative approach to enhance a state-of-the-art layout-aware circuit-level optimizer (GENOM-POF), by embedding statistical knowledge from an automatically generated gradient model into the multi-objective mu...