Abstract  This paper presents a design for a reconfigurable multiplier array. The multiplier is constructed using an array of 4 bit Flexible Array Blocks (FABs), which could be embedded within a conventional FPGA structure. The array can be configured to perform a number of 4n x 4m bit signed/unsigned binary multiplications. We have estimated that the FABs are about 35 times more efficient in ...

Using good properties of an optimal normal basis of type I in a finite field F2m , we present a design of a bit serial multiplier of Berlekamp type, which is very effective in computing xy. It is shown that our multiplier does not need a basis conversion process and a squaring operation is a simple permutation in our basis. Therefore our multiplier provides a fast and an efficient hardware arch...

Asynchronous circuits based on Current-Sensing Completion Detection (CSCD) are an efficient alternative to known dual rail coding techniques in terms of area required, operating speed and power consumption. New BiCMOS Current-Sensing Circuits (CSC’s) which fully support the advantages of CSCD are presented. Multiple localised CSC’s are studied and an example of a 4-bit parallel multiplier is in...

Reversible logic has attracted tremendous interest among the researchers in low power VLSI field due to their simple structure and improved energy efficiency. In this paper, the implementation of an 8-bit low power multiplier based on reversible gate technology is reported. The structure of the reversible gate multiplier consists of following components: the first part is the reversible partial...

In this paper we propose a modified probabilistic estimation bias (PEB) formula for fixed-width radix-4 Booth multiplier. The modified PEB formula estimates the same compensation value as the existing PEB formula without rounding operation. A bias circuit based on modified PEB formula generates one less carry-bit and involves less logic resources than the existing PEB circuit. The partial produ...

The main objective of the proposed work is implementing the 32 bit Vedic and Baugh-Wooley multiplication operation with Carry-Save methodology to reduce the average time and delay of operations. This system contain a high speed low power digital multiplier by using advantage of Vedic multiplication algorithms with a very efficient leakage control technique called multiple channel conventional m...

An efficient architecture of a reconfigurable Least/Most Significant Bit multiplier for Galois field where , is presented. The proposed multiplier can operate either as a most significant or as a least significant bit first multiplier. The value m, of the irreducible polynomial degree, can be changed and the value of M determines the maximum size that the multiplier can support. This architectu...

An asynchronous pipelined 32×32-bit iterative multiplier is presented in this paper. The multiplier supports 32×32-bit integer multiplication of both signed and unsigned operands. A 2-phase micropipeline latch controller is used which controls a 4-phase pipeline with standard transparent level sensitive latches. The design employs the modified Booth algorithm diminishing 8 bits at a time with a...

In this Paper, Urdhva tiryakbhyam Sutra is first applied to the binary number system and is used to develop digital multiplier architecture. This is shown to be very similar to the popular array multiplier architecture. This Sutra also shows the effectiveness of to reduce the NXN multiplier structure into an efficient 4X4 multiplier structures. Nikhilam Sutra is then discussed and is shown to b...