1.Problem of High-Speed Interface Macro Testing Because the function of the chip is guaranteed, the high-speed function test is important. Moreover, it is an important issue in LSI test how cheaply to do this test. The high-speed function test in an internal logical circuit can be tested by using BIST methodology and the output clock of PLL with a low-speed and low-cost ATE. However, the high-s...

In this paper a novel hierarchical DfT methodology is presented which is targeted to improve the delay fault testability for external testing and scanbased BIST. After the partitioning of the design into high frequency macros, the analysis for delay fault testability already starts in parallel with the implementation at the macro level. A specification is generated for each macro that defines t...

The main goal of this thesis was to develop an experimental environment for the test time minimization problem. It assumes Hybrid BIST architecture and targets System-on-Chip designs. The thesis is based on methodology developed during the work and demonstrates the feasibility of the proposed methodology together with experimental results. First two sections of this thesis explore the actuality...

We propose a procedure for designing an LFSRbased circuit for masking of unknown output values that appear in the output response of a circuit tested using LBIST. The procedure is based on reseeding of the LFSR to mask unknown output values while allowing fault effects to propagate. To determine the seeds, the output response of the circuit is partitioned into a minimal number of fragments, and...

A deterministic-partitioning technique and an improved analysis scheme for fault diagnosis in Scan-Based BIST is proposed. The incorporation of the superposition principle to the analysis phase of the diagnosis algorithm improves diagnosis times significantly; furthermore, the deterministic partitioning approach results in even further reductions in diagnosis times together with higher predicta...

Self-repairing system is alternative for fault tolerant systems. They lose efficiency when the circuit size increases, due to the extra hardware. In existing system, they used four spare cells for one working cell for cell replacement.In proposed system, there is no need to use spare cells permanently.In proposed system, we have taken RISC processor as a working cell for our consideration. BIST...

We propose several improvements to a previously proposed scheme of built-in test pattern generation for synchronous sequential circuits. The basic scheme consists of a parametrized structure for test pattern generation, where parameter values are determined randomly. The proposed improvements consist of an improved structure for test pattern generation that allows more flexibility in the determ...

In this letter a histogram-based BIST (Built-In Self-Test) approach for deriving the main characteristic parameters of an ADC (Analog to Digital Converter) such as offset, gain and non-linearities is proposed. The BIST uses a ramp signal as an input signal and two counters as a response analyzer to calculate the derived static parameters. Experimental results show that the proposed method reduc...

The paper presents a new approach to transparent BIST for wordoriented RAMs which is based on the transformation of March transparent test algorithms to the symmetric versions. This approach allows to skip the signature prediction phase inherent to conventional transparent memory testing and therefore to significantly reduce test time. The hardware overhead and fault coverage of the new BIST sc...