نتایج جستجو برای: all digital phase locked loop
تعداد نتایج: 2730969 فیلتر نتایج به سال:
Pulsed ultra-wideband (UWB) transceivers offer the potential for ultra-low-energy/bit operation because the signals are inherently duty-cycled. By eliminating components with long startup times, such as a phase-locked loop, all components in a pulsed-UWB transceiver can be disabled during the interval between pulses. This work focuses on an all-digital, pulsed-UWB transmitter that requires no a...
The tracking performance of non-linear amplifier based conventional second order phase locked loop (PLL) and charge pump phase locked loop have been examined numerically by solving the system equations in the presence of lognormal type of fading signal. Some analytical results for non-linear amplifier based conventional phase locked loop and charge pump phase locked loop are also incorporated t...
Technology advances have made gigabit signal a viable and attractive. A method to design IEEE 1394 based 1GHz Phase Locked Loop (PLL) system as frequency synthesizer with Low Phase Noise is proposed. A complementary LC oscillator is used to generate the 1GHz oscillation frequency and is divided into lower frequency clock by the feedback frequency divider. The architecture is type II third order...
This paper proposes a low-power all-digital phase-locked loop (ADPLL) with calibration-free ring oscillator (RO)-based injection-locking time to digital converter (TDC) for BLE applications. The RO is reused as the delay cell of TDC, and quantization step TDC always tracked period; hence no calibration needed in this architecture. We adopt tuning lower bandwidth so decrease power consumption in...
A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed adopts fall-edge-judgment phase adjuster and three-stage digitally controlled delay line to align the system input clock 0∘ output of DLL over wide frequency range, thus solving offset caused by skew. parallel-cascade configuration solve variable alignment pro...
This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-s...
The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. Based on this formula, the phase ...
We investigate laser high-order harmonic generation in the presence of interfering light. A relatively weak interfering pulse intersects the primary harmonic-generating laser pulse at the focus. The influence on the harmonic-generation process is studied at near-counterpropagating and at perpendicular angles. The interfering beam creates a standing intensity and phase modulation, which disrupts...
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