This application report describes a Reed Solomon decoder implementation on the TMS320C64x DSP family. Reed Solomon codes have been widely accepted as the preferred (ECC) error control coding scheme for ADSL networks, digital cellular phones and high-definition television systems. The reason for their widespread prevalence is their excellent robustness to burst errors. Programmable implementati...

Most versions of the Peterson-Gorenstein-Zierler (PGZ) decoding algorithm are not true bounded distance decoding algorithms in the sense that when a received vector is not in the decoding sphere of any codeword, the algorithm does not always declare a decoding failure. For a t-error-correcting BCH code, if the received vector is at distance i, i t, from a codeword in a supercode with BCH distan...

Design Introduction Our design target was to build a low-cost, high-performance H.264 decoder with a prototype H.264 decoder created using multiple small FPGAs. H.264 is a computationally complex, advanced video standard for achieving high compression ratios. To cater to the needs of high throughput applications such as HDTV, which requires 216,000 macroblocks/second of throughput, designers us...

This paper presents an approach to vector quantization of sources exhibiting intervector dependency. We present the optimal decoder based on a collection of received indices. We also present the optimal encoder for such decoding. The optimal decoder can be implemented as a table look-up decoder, however the size of the decoder codebook grows very fast with the size of the collection of utilized...

Since current Text-to-Speech (TTS) synthesizers are mostly based on a technique known as synthesis by concatenation, the implementation of a high quality TTS requires huge storage space for a large number of speech segments. In order to compress the database in the TTS system, the use of speech coders would be an efficient solution. Waveform Interpolation (WI) has been shown to be an efficient ...

In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three ...

As a technology to read brain states from measurable brain activities, brain decoding are widely applied in industries and medical sciences. In spite of high demands in these applications for a universal decoder that can be applied to all individuals simultaneously, large variation in brain activities across individuals has limited the scope of many studies to the development of individual-spec...

Let Φ(ω), ω ∈ Ω, be a family of n ×N random matrices whose entries φi,j are independent realizations of a symmetric, real random variable η with expectation IEη = 0 and variance IEη2 = 1/n. Such matrices are used in compressed sensing to encode a vector x ∈ IR by y = Φx. The information y holds about x is extracted by using a decoder ∆ : IR → IR . The most prominent decoder is the `1-minimizati...

This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber-optic rates and outputs to be delivered at correspondingly high rates with minimum delay. Parallel processing architecture results in...

Reliability and flexibility are among the key required features of a framework used to model a system. Existing approaches to design resource-constrained, soft-real time systems either provide guarantees for output quality or account for loss in the system, but not both. We propose two independent solutions where each modeling technique has both the above mentioned characteristics. We present a...