A process, voltage and temperature (PVT) sensors with dynamic voltage selection are proposed for environmental management in the ultra-low voltage dynamic voltage and frequency scaling (DVFS) system. The process and voltage (PV) sensors initially monitor the process variation. With known process information, PV sensors can real-time provide voltage variation status. The temperature sensor has s...

Negative Bias temperature Instability (NBTI) has become one of the major sources of degradation in scaled PMOS devices, affecting the yield and reliability of circuits as well as the power and performance. As the oxide thickness decreases with each technology generation, increased oxide electric field and higher current densities degrade the performance and lifetimes of devices (especially PMOS...

This paper presents a dynamic voltage and frequency scaling methodology for long-term operation, using fault-tolerance to prevent failures. The DVFS methodology allows a dual-mode operation, targeting high performance or low-power operation modes, and using an on-line circuit monitoring with aging-aware fault-tolerance to prevent errors during a long-term operation. Fail-safe operation is achie...

In this research, the probabilistic model of the random variations in nanoscale MOSFET’s high frequency performance defined in term of variation in gate capacitance, has been proposed. Both random dopant fluctuation and process variation effects which are the major causes of the MOSFET’s high frequency characteristic variations have been taken into account. The nanoscale MOSFET equation has bee...

The work developed consists in a power or performance optimization methodology, for long-term operation, using global and local aging aware performance sensors. Methodology allows circuits to be dynamically optimized, during their life-time, according with one of two possible needs: (1) restrict power consumption, by reducing power-supply voltage to the minimum value that prevents errors from h...

The subthreshold regime is a critical biasing space as it enables minimum energy operation for logic circuits [1]. However, practical systems rely heavily on SRAMs, which conventionally limit the minimum VDD to above Vt. SRAMs often dominate the total die area and power, and minimizing their energy requires scaling VDD as low as possible. In this work, a 256kb SRAM in 65nm CMOS is presented tha...

Physically Unclonable Functions (PUFs) provide a unique signature for integrated circuits (ICs), similar to a fingerprint for humans. They are primarily used to generate secret keys, hereby exploiting the unique manufacturing variations of an IC. Unfortunately, PUF output bits are not perfectly reproducible and non-uniformly distributed. To obtain a high-quality key, one needs to implement addi...

In this paper we present the implementation results for all five SHA-3 third round candidate algorithms, BLAKE, Grøstl, JH, Keccak, and Skein in a standard-cell-based ASIC realized using 65nm CMOS technology. The ASIC includes two sets of implementations developed independently and with different optimization targets, and includes a reference SHA-2 implementation as well. We believe that having...