Beginning with a brief review of CMOS scaling trends from 1 m to 0.1 m, this paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the limit of scaling. The fundamental limiting factors are electron thermal energy, tunneling leakage through gate oxide, and 2D electrostatic scale length. Both the standby power and the active power of ...

A new design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. This design approach applies CFA OTA as input stage cascaded with class AB cross-coupled buffer stage. The performance parameters of CMOS CFOA such as bandwidth, slew rate, settling time are extensively improved compared with conventional CFOA. These parameters are very important in high frequency ...

Apart from the ongoing debate about using CMOS active pixel sensors (APS) or CCD imagers for today’s consumer and commercial applications the emerging biomedical market presents new opportunities to CMOS APS. Prominent examples addressing distinct issues in life style and health care are the possibilities to restore vision through a sub-retinal CMOS imager implant and to fabricate a low-cost in...

In this paper we present robust and high performance static ultra low-voltage CMOS binary logic. The delay of the ultra low-voltage logic presented are less than 10% of the delay of standard CMOS inverters. The logic gates presented are designed using semi floating-gate transistors and a current boost technique. The boolean gates resemble domino CMOS. The performance and robustness of different...

in this paper, a new structure possessing the advantages of low-power consumption, less hardware and high-speed is proposed for fuzzy controller. the maximum output delay for general fuzzy logic controllers (flc) is about 86 ns corresponding to 11.63 mflips (fuzzy logic inference per second) while this amount of the delay in the designed fuzzy controller becomes 52ns that corresponds to 19.23 m...

|Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or less than the time of ight delay of the signal through the interconnect. In this discussion, a linear resistor model is used to approximate the CMOS driver stage, and the CMOS receiver is modeled as a capacitor. A closed form e...

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in m...