Designers are increasingly using VHDL for high-level modeling. However, their task is hindered by the lack of object-oriented and genericity features in the language. Experience in programming languages shows that these features significantly aid management of complexity in large designs and promote re-use of modules. SUAVE extends VHDL by adapting several object-oriented and genericity feature...

Considering the importance of real time filtering, a comparison was done between two prominent window techniques known for digital filtering. A 16 tap digital band pass FIR filter is designed for each design technique (Kaiser and Hamming) and implemented over FPGA. The Simulink model of the filter confirms the correctness and other properties of the digital filter. Further a hardware descriptiv...

The tool to be presented in the panel deals with validation of VHDL descriptions at the early phase of the design of a digital system. Our approach consists in generating test data from a given VHDL behavioral description. The validation is achieved by comparing the results obtained using the simulation of the VHDL description within the test data and the results which should have been obtained...

This paper will describe the development of a prototype software toolbox that can analyze and process a Simulink block diagram model in order to produce a VHDL representation of the model. The derived VHDL model will consist of a combination of behavioural, RTL and structural definitions mapped directly from the Simulink model. This approach may enable a user to develop and simulate a digital c...