An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T cells, power of hold mode reduced significantly. The stability parameters are calculated using butterfly method also N-curve method. Proposed achieves better write margin slightly less read than SRAM. technique consumes 790 PW mode, w...

Memory circuits such as static random-access memory (SRAM) and dynamic (DRAM) form an integral part of system design contribute significantly to system-level power consumption. operating speeds dissipation have become important parameters due the explosive growth battery-operated appliances increased integration Hence SRAMs with different topologies are examined in terms like propagation delay,...

This paper proposes new methods for SRAM cell design in FinFET technology. One of the most important features of FinFET is that the independent front and back gates can be biased differently to control the current and the device threshold voltage. By controlling the back gate voltage of a FinFET, a SRAM cell can be designed for low power consumption. This paper proposes a new 8T (8 transistors)...

This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. The key idea is thus to realize and depl...

Deep Sub-Micron SRAM Design for Ultra-Low Leakage Standby Operation by Huifang Qin Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California, Berkeley Professor Jan M. Rabaey, Chair Suppressing the standby current in memories is critical in low-power design. By lowering the supply voltage (VDD) to its standby limit, the data retention voltage (DRV...

Increased leakage current and device variability are the major challenges with CMOS technology scaling. Since Static Random Accessed Memory (SRAM) is often the largest component in the embedded digital systems or System-on-Chip (SoC), it is more vulnerable to those challenges. To effectively reduce SRAM leakage and/or active power, supply voltage (VDD) is often scaled down during standby and/or...

The binary values processed and stored at the intermediary stages of an algorithm are often highly correlated. Motivated in part by this observation and the ever-increasing challenge of power density for Integrated Circuit (IC) systems, a novel reconfigurable memory framework is proposed in this thesis which builds upon traditional low power techniques such as voltage scaling in order to achiev...

Outline zIntroduction zRelated Work zSleepy stack zSleepy stack logic circuits zSleepy stack SRAM zLow-power pipelined cache (LPPC) zSleepy stack pipelined SRAM zConclusion

We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 6T SRAM operates at 0.42 V, in which an FS corner can be compared as much as 0.14 V or more. key w...

A closed loop self-tuning 256kb 6T SRAM with 0.38V-1.2V extended operating range using combined read and write assists and canary-based VMIN tracking is presented. 337X and 4.3X power reductions are achieved using multiple assists and VMIN tracking, respectively; combining both saves 1444X in active power and 12.4X in leakage at the 0.38V. Keywords—self-tuning SRAM; combined assists; canary SRA...