This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in onchip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 3011s. Inactive memor...

This paper gives a brief introduction to the application-dependent FPGA testing. In comparison with the conventional application-independent FPGA testing whose objective is to test the resources of a FPGA chip as exhaustively as possible, application-dependent FPGA testing is only performed on the resources used by a specific application implemented on the FPGA. The multi-configuration strategy...

We consider implementing FPGAs using a standard cell design methodology, and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [Rose et al. 2012] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can subsequently be synthesized ...

There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Tree, Bipartite Graph, and Mesh interconnection sch...

Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough. Partitionning a NoC on multi-FPGA requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. We pres...

This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshakecomponent-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an areaefficient architecture of an FPGA that is suitable for handshake-componentbased asynchronous circuit. Moreover, the Four-Phase Dual-Rail en...

Self-Timed FPGA Systems p. 21 XC6200 Fastmap Processor Interface p. 36 The Teramac Configurable Computer Engine p. 44 Telecommunication-Oriented FPGA and Dedicated CAD System p. 54 A Configurable Logic Processor for Machine Vision p. 68 Extending DSP-Boards with FPGA-Based Structures of Interconnection p. 78 High-Speed Region Detection and Labeling Using an FPGA Based Custom Computing Platform ...

system has very much importance because it will increase performance and accuracy. The fault injection method is used to find out the fault tolerance of a system. This method is valuable and attractive. In this paper fast FPGA based fault injector for memory unit is introduced. In previous FPGA based fault injection methods the response according to the fault injection is send to the observatio...