In this paper, an efficient design scheme for implementation of the Proportional-IntegralDerivative (PID) controller using Field Programmable Gate Array (FPGA) technology is presented. It is efficient scheme in the sense dynamic power system, effective cost over other digital implementation techniques and etc. The VHDL (VHSIC Hardware Description Language; VHSIC: very-high-speed-integrated circ...

In reconfigurable computing systems, are evolving rapidly, due to their flexibility and high performance. In this paper, we focus on communication cost between partitions in order to develop an algorithm to solve temporal partitioning problems for reconfigurable architecture. In fact, this algorithm optimizes the transfer of data required between design partitions. The proposed algorithm was te...

While FPGA accelerator boards and their respective high-level design tools are maturing, there is still a lack of multi-FPGA applications, libraries, not least, benchmarks reference implementations towards sustained HPC usage these devices. As in the early days GPUs HPC, for workloads that can reasonably be decoupled into loosely coupled working sets, multi-accelerator support achieved by using...

In the Reconfigurable System-On-a-Chip (RSOC), an FPGA core is embedded to improve the design flexibility of SOC. In this paper, we demonstrate that the embedded FPGA core is also feasible for use in implementing the proposed hybrid pattern Built-In Self-Test (BIST) in order to reduce the test cost of SOC. The hybrid pattern BIST, which combines Linear Feedback Shift Register (LFSR) with the pr...

New markets are emerging for the fast growing field-programmable gate array (FPGA) industry. Standard and fair benchmarking practices are necessary to evaluate FPGA systems and determine their potential to support target applications. This paper provides an extensive survey of FPGA benchmarks in both academia and industry.