The number of IPs integrated in a chip is growing proportional to the number of gates available on the chip. Standards-compliant IP designs have been gaining momentum as a viable alternative to full custom in-house IP design. The notion is that it will be more efficient to port a third party IP designed based on industry standards than a non-standards-based IP. IP-based design is not a new conc...

An elation of a design 2 is an automorphism y of Sf fixing some block X pointwise and some point x on X blockwise. Luneburg [4] and I [2] have proved results which state that a design admitting many dations and having additional properties must be the design of points and hyperplanes of a finite desarguesian projective space. In this note, additional results of this type will be proved and appl...

Setting design specifications (targets) is a critical task in the early stages of a design process. Flexible targets can accommodate uncertainty and changes in design by postponing design commitments and preserving design freedom. In this work, a new method is developed for obtaining a ranged set of design specifications that meets design criteria while incorporating design space heterogeneity,...

A quasi-symmetric design (QSD) is a 2-(v, k, λ) design with intersection numbers x and y with x < y. The block graph of such a design is formed on its blocks with two distinct blocks being adjacent if they intersect in y points. It is well known that the block graph of a QSD is a strongly regular graph (SRG) with parameters (b, a, c, d) with smallest eigenvalue −m = −k−x y−x . The classificatio...

The main emphasis in developing DOS has been on achieving low crosstalk (CT). CT in the order of -30 dB is acceptable in conventional DOS and below that value is hard to achieve. Relatively low drive voltage (or power requirements) is also necessary to optimized DOS. This paper depicts the design of Y-branched digital optical switches (DOS) with optimized on-chip area coverage, reduced driving ...

Let r, s, q,m, n ∈ N be such that s ≥ r ≤ q. Let Y be a fibered manifold with m-dimensional basis and n-dimensional fibers. All natural affinors on (J(Y,R)0) are classified. It is deduced that there is no natural generalized connection on (J(Y,R)0). Similar problems with (J(Y,R)0) instead of (J(Y,R)0) are solved.

Motivated b y improving FPGA performance, we propose a new three-dimensional (3U) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing y i e l d , and raise seuera1 physical-design issues in the new 30 paradigm. Our techniques also have good implications for resource utilization, physical size, and power consumption.