The RACE-Hypercube Processor is a highly parallel signal processor with fourteen degrees of freedom in selecting parallel operations. The fourteen degrees of freedom include the ability to select the 1) number of very long instruction word (VLIW) slots, 2) number and type of application specific instructions, 3) number and type of application specific processing element (PE) hardware assists, 4...

Emerging applications in the mobile and automotive industries can benefit from a solution which can segment an image into objects. Although originally not developed for these applications, Objectbased Motion Estimation (OME) is an algorithm which provides such a segmentation. In this paper we map this algorithm on an Application Specific Instruction Processor (ASIP) based on a Very Long Instruc...

In this paper, a general fault-tolerant framework adopting a more rigid fault model for VLIW data paths is proposed. The basic idea used to protect the data paths is that the execution result of each instruction is checked immediately and if errors are discovered, the instruction retry is performed at once to overcome the faults. An experimental architecture is developed and implemented in VHDL...

This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the development cycle, and to use the powerful FPGA resources in order to increase real-time performance. We present a modular VLIW VHDL processor model with a variable instructio...

In order to improve the performance for real-time application, current digital signal processors use VLIW architectures to increase the degree of instruction level parallelism (ILP). There exist two factors making the ILP barriers; one is the hardware resource limitation for all parallel instructions. Another is the dependence relations between instructions. For coping these hazards, in this pa...

In this paper the implementation of the test strategy in a so-called Very Long Instruction Word Transport Triggered Architecture (VLIW-TTA) is discussed. The complete test strategy is derived referring to the results of test synthesis, carried out in the early phase of the design. It takes the area/throughput parameters into account. The test strategy, exploiting the regularity and modularity o...

Out of order (OoO) processors use complex logic to maximize Instruction Level Parallelism (ILP). However, since the resulting dynamic instruction schedule of many applications seldom changes, it is reasonable to store and reuse the schedule instead of reconstructing it each time. To do this, we propose Yoga, a hybrid VLIW/OoO processor that dynamically stores instruction schedules generated whi...

Disclaimer: " The contents of this document are scribe notes for The University of Texas at Austin EE382V Spring 2007, Computer Architecture: User System Interplay *. The notes capture the class discussion and may contain erroneous and unverified information and comments. This paper comes from industry. Transmetta's Crusoe microprocessor is a VLIW microprocessor that along with a software layer...

In this paper, we present the rationale and design of the Delft reconfigurable and parameterized VLIW processor called ρ-VEX. Its architecture is based on the Lx/ST200 ISA developed by HP and STMicroelectronics. We implemented the processor on an FPGA as an open-source softcore and made it freely available. Using the ρ-VEX, we intend to bridge the gap between general-purpose and application-spe...

This paper describes a 51.2 GOPS video recognition processor that provides a cost effective device solution for vision based ICC (Intelligent Cruise Control) applications. By integrating 128 4-way VLIW processing elements into a single chip based on a SIMD linear array architecture, and operating in 100 MHz, the processor achieves to provide a computation power enough for a weather robust lane ...