this report shows the survey of reliability of 3D IC manufactory and its robustness. Firstly, we consider the reliability of the manufactory of 3D IC. The process-induced thermal stresses around TSVs raise serious reliability issues such as Si cracking and performance degradation of devices. Finite element analysis (FEA) combined with analytical methods is introduced to investigate this issue, ...

In this paper, we attempt to understand the physico-chemical changes that occur in devices during device "burn-in". We discuss the use of low frequency dielectric spectroscopy to detect, characterize and monitor changes in electrical defects present in the dielectrics of through silicon vias (TSV) for three dimensional (3D) interconnected integrated circuit devices, as the devices are subjected...

3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The reduction in the number of 3D vias obtained with the adoption of serial vertical connections can relieve the routing congestion of the 3D system...

Scorpion sting-induced human envenomation provokes an intense inflammatory reaction. However, the mechanisms behind the recognition of scorpion venom and the induction of mediator release in mammalian cells are unknown. We demonstrated that TLR2, TLR4 and CD14 receptors sense Tityus serrulatus venom (TsV) and its major component, toxin 1 (Ts1), to mediate cytokine and lipid mediator production....

A significant physical design challenge in both high-performance 3D integrated circuits and lowpower 3D systems-on-chip is to guarantee system-wide power and signal integrity. This chapter provides an overview of these challenges with emphasis on through-silicon via (TSV)-based 3D ICs. Different TSV types and their implications to power/signal integrity are first discussed. In the next section,...

In the semiconductor industry, 3D integration using through-silicon via (TSV) has been considered to be a promising way for improving performance and density instead of conventional device scaling. Si wafer thinning is an important technology in 3D stacking. Since the ultra-thin device provides low aspect ratio TSV, several advantages can be expected, such as reduced parasitic RC delay, lower p...

BACKGROUND The Pacific white shrimp, Litopenaeus vannamei, is a worldwide cultured crustacean species with important commercial value. Over the last two decades, Taura syndrome virus (TSV) has seriously threatened the shrimp aquaculture industry in the Western Hemisphere. To better understand the interaction between shrimp immune and TSV, we performed a transcriptome analysis in the hepatopancr...

Theoretical studies in the 1980s [1, 2] suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple tiers of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose plac...

Heterogeneous manycore architectures are the key to efficiently execute compute- and data-intensive applications. Through silicon via (TSV)-based 3D system is a promising solution in this direction as it enables integration of disparate computing cores on single system. However, achievable performance conventional through-silicon-via systems ultimately bottlenecked by horizontal wires (wires ea...