Simulation is the most viable solution for the functional verification of SoC. The acceleration of simulation with multi-FPGA is a promising method to comply with the increasing complexity and large gate capacity of SoC. The most time-consuming factor of multi-FPGA simulation accelerator is signal transfer time between simulator and multi-FPGA system. This paper proposes a performance driven de...

In order to realize the requirements of low latency and power consumption in real-time path planning for private vehicles, this paper designs an FPGA accelerator based on road information Dijkstra's shortest algorithm, which is applied system vehicle edge computing. The designed using Xilinx High-Level Synthesis (HLS) compiler implemented programming logic a Zynq FPGA. experiment carried out ci...

The current work is aimed to fabricate a pulse generator to meet the requirements of control and process signals to be applied on to several basic constituting functional units of a radar system. The functional units of Radar system includes Exciter, Receiver, Radar Controller, TCSG and Duplexer Antenna.The synchronized pulses generated are operate on functional units is accomplished by generat...

Federated learning has solved the problems of data silos and fragmentation on premise satisfying privacy. However, cryptographic algorithms in federated brought significant increase computational complexity, which limited speed model training. In this paper, we propose a hardware/software (HW/SW) co-designed field programmable gate array (FPGA) accelerator for learning. Firstly, analyzed time c...

In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad range of benchmark circuits. To validate our design approach, FPGA layout tools which target devices with less that 100% logic capacity have been developed to augment existing approaches that target fully-utilized devices. These to...

Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of convolution codes, at the receiver end Viterbi Decoder is being employed. The parameters of Viterbi algorithm can be changed to suit a specific application. The high speed and small area are two important design parameter...