Systolic arrays are a family of parallel computer architectures capable of using a very large number of processors simultaneously for important computations in applications such as scientific computing and signal processing. Systolic array architecture has contains 1 full adder and the latency with m per cell while semi-systolic array architecture has contains m/2 latency. The proposed multipli...

This paper describes an implementation of a novel systolic array for sequence alignment on the SPLASH reconfigurable logic array. The systolic array operates in two phases. In the first phase, a sequence comparison array due to Lopresti [2] is used to compute a matrix of distances which is stored in local RAM. In the second phase, the stored distances are used by the alignment array to produce ...

Adaptive beamformers for sensor arrays, are widely used in RADAR, SONAR and communications applications in order to increase the directivity of the sensor system to the target, while suppressing the interfering signals by adapting the radiation pattern of the antenna array. A signal processing hardware accomplishes the beamforming by adjusting the weights of the sensor array system. Eventhough ...

Several systolic Kalman lters have appeared in the literature, with often complex hardware constructs to accomodate the algorithmic `anomalies'. Here, we follow a di erent route by working the original information lter into a so-called `Jacobi-type' algorithm, which is much more regular and directly ts onto a common and general Jacobi-type systolic array. The e ciency of the resulting systolic ...

It is our opinion that the system-on-chip, all-in-one approach to parallel digital signal processing combining the homogeneous processor array with large amounts of data memory, will be the core of future embedded digital signal processing applications. In this paper we present two radical approaches to efficient system-on-chip (SoC) design with homogeneous processor arrays for real-time applic...

This paper presents an architecture for programmable systolic arrays that provides simple and eecient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 1504-processor implementation could provide 5 GOPS of systolic co-processing power on a single board.

In this paper, we present a performance comparison between linear recursive variable expansion (RVE) and linear systolic array implementations of the Smith‐Waterman (S‐ W) algorithm. The results demonstrate that the temporal performance of linear RVE implementation is 2.11 to 3 times better than the traditional linear systolic array implementation at the spatial co...

In this paper we propose a synergy of processing on parallel processor arrays (systolic or SIMD) and multithreading named multithreaded systolic computation. Multithreaded systolic computation enables simultaneous execution of independent algorithm data sets, or even different algorithms, on systolic array level. This approach results in higher throughput and improved utilization of programmabl...

This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation of this Systolic Shared Register architecture; a working 470-processor prototype system performs 108 MOPS. A 32-chip, 1504-processor implementation could provide 5 GOPS of systolic co-processing power on a single board.