Abstract— The strong demand for complex and high performance embedded system-on-chip (SoC) requires quick turn around design methodology and high performance cores. Thus, there is a clear need for new methodologies supporting efficient and fast design of these systems on complex platforms implementing both hardware and software modules. In this paper, we describe a novel scalable core-based (SC...

The power specification of a chip is generally developed during the product conception stage. Engineers select technology libraries, IPs, and make architectural decisions by weighing them against the impact on the power budget. In this paper, we present a knowledge-base (KB) system for pre-design chip power estimation, which uses post-layout power information from previous designs. KB rules are...

Abstract— The wavelength routed optical network (WRON) is a promising optical interconnection architecture that can be integrated into a System-on-Chip (SoC) with an intention to replace traditional wire-connected on-chip micro-networks which pose severe bandwidth limitations on future super large SoC chips. In this paper, we present a new recursive architecture, the Recursive Wavelength Routed...

Based on product related scenarios, the impact of on-chip inductance on power supply integrity is analyzed. The impact of varying current profiles is shown to be minimal. In a regular power grid with regular bump connections, the impact of on-chip inductance on the cycle average of the supply voltage can be neglected, even for a worst case estimation of on-chip inductance. Whereas, the maximum ...

Today’s System-on-Chip typically embeds memory IP cores with very large aggregate bit count per SoC. This trend requires using dedicated resources to increase memory yield, while containing test & repair cost and minimizing time-to-volume. This paper summarizes the evolution of such yield optimization resources, compares their trade-offs, and concentrates on on-chip Infrastructure IP. To maximi...

A two-level test data compression technique is presented to reduce both the test data and the test time for System on a Chip (SOC). The level one compression is achieved by Huffman coding for the entire SOC. The level two compression is achieved by broadcasting test patterns to multiple cores simultaneously. Experiments on the d695 benchmark SOC show that the test data and test time are reduced...

The increasing gap between design productivity and chip complexity, and emerging systems-on-a-chip (SoC) have led to the wide utilization of reusable intellectual property (IP) cores. Educators’ responsibility is to provide future generations of SoC architects with knowledge necessary for successful design and use of IP cores, and to offer them a system perspective including both hardware and s...

With many system bus alternatives in telecom, signal processing, etc, chip designers face the prospect of having to support multiple interfaces to meet interconnect requirements. Designers must then build next-generation chip architectures that deliver reliable interconnect architectures and ensure interworking between SoC heterogeneous IP blocks. In this article we show how formal verification...

Today’s system-on-chip (SoC) systems must be designed as quickly as possible by integrating IP blocks from diverse suppliers. In this paper, we present a new automatabased algorithm that automatically synthesizes glue logic for SoC fabrication and Transaction-level modelling (TLM) transactors for SoC modelling. Our approach introduces a new encoding for state variables which captures data conse...

In this paper, we implement the arctangent computation in Histograms of Oriented Gradients (HOG) descriptor extraction, targeting realtime pedestrian recognition System-on-Chip (SoC) design. Experimental results with 90nm CMOS technology shows the feasibility of the hardware architecture for SoC design.