This paper presents a fully integrated CMOS Vband Injection-Locked Power Amplifier (ILPA) for phase and frequency modulated millimeter-Wave (mm-Wave) transmitter. At mm-Wave frequency, multi-stage PAs are usually employed to achieve enough power gain due to low power gain of CMOS transistor even though it has low power efficiency. This work investigates mm-Wave ILPA for constant envelope modula...

An ultra-wideband low noise amplifier for cognitive radio applications covering 50 MHz to 10 GHz is designed in a 65-nm CMOS technology. A three-stage dc-coupled common source amplifier with RC degeneration at the last stage optimizes the gain, linearity and output gain-phase balancing. Throughout the covered band, the simulated voltage gain is >23.3 dB whereas the noise figure is <3.4 dB. The ...

Methodology for selection index updating was developed to allow multistage selection. The program determines truncation points for each stage of selection that will maximize either profit or the ratio of aggregate economic gain to cost (R = delta H/C). Either maximum profit or R may be attained by reducing the cost of performance testing in later stages of a multistage program. In order to elim...

Currently, there are two demands in RF front-end design such as multi-standard application and low power consumption. However, it is difficult to satisfy these demands simultaneously. Therefore, two design techniques are explained in this paper, respectively. In this paper, two RF circuits, a variable gain LNA and low power folded RF frontend, are designed. At first, a variable gain LNA (VG-LNA...

A multi-output second generation current conveyor (MOCCII), that can be used to realized first, second and third generations current conveyors, is proposed. The MOCCII consists of a CMOS differential stage for the voltage input, push-pull stage and the improved cascode current mirrors for the current output. Feedback techniques are proposed in order to provide a voltage gain of 0.991, a current...

This paper proposes and studies the effects of a dual-stage compensation technique for achieving greater than 100 kHz crossover frequency of a single pole system converting from 48 V to 1.2 V. By placing a separate non-inverting gain stage after the error amplifier, the necessary gain-bandwidth of the op amp can be significantly reduced allowing for high crossover frequency and good transient r...

In this study, we designed a Ka-band two-stage differential power amplifier (PA) using 65 nm RFCMOS process. To enhance the output of PA, three-stack structure was utilized in stage, while driver stage PA with common-source to minimize consumption stage. The layout an external gate capacitor for stacked split maximize performance transistor. With proposed capacitor, gain, power, and power-added...

A 5GHz low power consumption LNA has been designed here for the receiver front end using 90nm CMOS technology. The ‘current reuse’ technique has been used here to reuse the bias current for two amplifier stages stacked upon each other. An inverter type amplifier acts the second stage to a common source first stage thereby giving a good gain for the amplifier. The gain achieved is around 13dB wi...

A fully differential programmable gain amplifier (PGA) with constant transfer characteristic and very low power consumption is proposed and implemented in a 130 nm CMOS technology. The PGA features a gain range of 4 dB to 55 dB with a step size of 6 dB and a constant bandwidth of 10–550 kHz. It employs two stages of variable amplification with an intermediate 2nd order low-pass channel filter. ...