A novel nine transistor (9T) CMOS SRAM cell design at 32nm feature size is presented to improve the stability, power dissipation, and delay of the conventional SRAM cell along with detailed comparisons with other designs. An optimal transistor sizing is established for the proposed 9T SRAM cell by considering stability, energy consumption, and write-ability. As a complementary hardware solution...

Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for SRAM which occupies large transistor count in most state-of-the-art chip designs. We propose a novel ultralow leakage SRAM design whi...

Static RAM cells are widely used for industrial and scientific subsystems, automotive electronics, etc .The power consumption of SRAM values depend on how frequently it is accessed. It can be power-hungry as dynamic RAM, when used at high frequencies. Integrated circuits consume higher watts at full bandwidth. In non-volatile SRAM and asynchronous SRAM, Power consumption limits its application....

In this paper we propose analytical models for estimating the leakage power in CMOS based SRAM designs. We identify the transistors that contribute to the leakage power in each SRAM sub-circuit as a function of the operation (read/write/idle) on the SRAM and develop parameterized leakage power models in terms of the high level design parameters and transistor widths. The models take number of r...

In this report, we aim to realize an ultra-low-power Static Random Access Memory (SRAM) realized on a different logic conversion block from traditional 6T SRAM, referring to Source-Coupled-Logic (SCL) based topology. It enables low supply voltage operation possible to effectively reduce power consumption according to the relationship, . The supply voltage in this report is lowered to 0.5V and t...

An ultra-low leakage static random-access memory (SRAM) cell structure with 8 transistors is proposed in this paper. Compared to the 6T SRAM and other existing 8T cells, power of hold mode reduced significantly. The stability parameters are calculated using butterfly method also N-curve method. Proposed achieves better write margin slightly less read than SRAM. technique consumes 790 PW mode, w...

Memory circuits such as static random-access memory (SRAM) and dynamic (DRAM) form an integral part of system design contribute significantly to system-level power consumption. operating speeds dissipation have become important parameters due the explosive growth battery-operated appliances increased integration Hence SRAMs with different topologies are examined in terms like propagation delay,...

This paper proposes new methods for SRAM cell design in FinFET technology. One of the most important features of FinFET is that the independent front and back gates can be biased differently to control the current and the device threshold voltage. By controlling the back gate voltage of a FinFET, a SRAM cell can be designed for low power consumption. This paper proposes a new 8T (8 transistors)...

This paper presents a method based on dual threshold voltage assignment to reduce the leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. The key idea is thus to realize and depl...

Deep Sub-Micron SRAM Design for Ultra-Low Leakage Standby Operation by Huifang Qin Doctor of Philosophy in Engineering Electrical Engineering and Computer Sciences University of California, Berkeley Professor Jan M. Rabaey, Chair Suppressing the standby current in memories is critical in low-power design. By lowering the supply voltage (VDD) to its standby limit, the data retention voltage (DRV...