This paper proposes a System-on-ProgrammableChip (SoPC) architecture to implement a stereo matching algorithm based on the sum of absolute differences (SAD) in a FPGA chip which can provide 1396×1110 disparity maps at 30 fps speed. The hardware implementation involves a 32bit Nios II microprocessor, memory interfaces and stereo matching algorithm circuit module. The stereo matching algorithm co...

This paper presents the architecture and implementation of a 2.5 Gbps Programmable Point-toPoint-Protocol Processor (P) on a Virtex II FPGA. A 32bit wide pipelined processor circuit is implemented for layer 2 frame processing and a Leon processor core is embedded for higher layer PPP control protocol processing. An AMBA bus interface is used to interlink the Leon processor to the hardware frame...

Introduction Video and image processing applications are typically very computationally intensive. Given the increasing processing demands, the parallel processing capabilities of Altera® programmable logic devices make them an attractive implementation option for highly repetitive tasks found in video and imaging functions. Instead of using multiple programmable digital signal processors, a si...

Electric power is mainly derived from a combination of an engine and a motor. The motor converts electrical power into mechanical energy, which is widely used in home appliances and industrial mechanical tools. When addressing specific applications, motor-driven tools generally need to make speed changes or have accurate positioning. In these applications, it is necessary to have a highly effic...

Today, a significant number of embedded systems focus on multimedia applications with almost insatiable demand for low-cost, high performance, and low power hardware cosumption. In this paper, we present a re-configurable and generic hardware platform for image and video processing. The proposed platform uses the benefits offered by the Field Programmable Gate Array (FPGA) to attain this goal. ...

Multicore processors get more and more popular, even in embedded systems. Unfortunately, these types of processors require a special kind of programming technique to offer their full performance, i.e. they require a high thread-level parallelism. In this paper we evaluate the performance of different configurations of the same processor core within an SoPC: a single threaded single core, a mult...

This paper discusses a novel embedded system-on-chip 3D localization and mapping (eSoC-LAM) implementation, that followed co-design approach with the primary aim of being deployed in small system on programmable chip (SoPC), Intel’s (a.k.a Altera) Cyclone V 5CSEMA5F31C6N, available Terasic’s board DE1-SoC. computer incorporates an 800 MHz Dual-core ARM Cortex-A9 FPGA 85k logic elements 4450 Kbi...

With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent confidentially over the network without fear of hackers or unauthorized access to it. This makes security implementation in networks a crucial demand. Symmetric Encryption Cores provide data protection via the use of sec...