The present work considers electrothermal simulation of LDMOS devices and associated nonequilibrium effects. Simulations have been performed on three kinds of LDMOS: bulk Si, partial SOI and full SOI. Differences between equilibrium and nonequilibrium modeling approaches are examined. The extent and significance of thermal nonequilibrium is determined from phonon temperature distributions obtai...

In the literature frontal crashes typically have been classified as full, large overlap, or small overlap impacts (SOI) in accordance with the degree of frontal area involvement. These classifications implicitly refer to the degree of longitudinal structure engagement during impact. While full and large overlap impacts have received considerable attention, SOI has undergone limited analyses thr...

A correlation between the gated-diode R-G current and the performance degradation of SOI n-channel MOS transistor after F-N stress test has been demonstrated in this paper. Due to increase of interface traps after F-N stress test, the generation-recombination (R-G) current of the gateddiode in the SOI-MOSFET architecture increases while the performance characteristics of MOSFET transistor such ...

This paper describes applications of Silicon on Insulator (SOI) technology to high performance onchip memories (e.g. SRAMs and register files etc.).The primary focuses are on the important and unique issues in SOI technology such as performance gain, history effect, power reduction, pulsewidth control and self-heating. The effects on the interconnect performance and reliability are also discuss...

The southern oscillation index (SOI) is a characteristic of the El Niño phenomenon. SOI monthly averaged data is analyzed for the time interval 1866-2000. The tail of the cumulative distribution of the fluctuations of SOI signal is studied in order to characterize the amplitude scaling of the fluctuations and the occurrence of extreme events. Large fluctuations are more likely to occur than the...

Well-behaved Ge quantum well (QW) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) were fabricated on silicon-on-insulator (SOI) substrate. By optimizing the growth conditions, ultrathin fully strained Ge film was directly epitaxially grown on SOI at about 450 °C using ultra-high vacuum chemical vapor deposition. In situ Si2H6 passivation of Ge was utilized to form a high...

The proliferation of both Partially Depleted SiliconOn-Insulator (PD-SOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between dynamic circuit styles and PD-SOI complicate testing. This paper describes the issues of testing domino circuits fabricated in SOI technology and...

This paper describes the characteristics comparison of bulk FINFET and SOI FINFET. The scaling trend in device dimension require limit on short channel effect through the control of subthreshold slope and DIBL characteristics.It can be achieved by proper device design. The subthreshold characteristics are plotted with the variation of gate voltage for different doping profile .This paper also c...

1. Abstract We estimate the soft error rates of FD-SOI structures according to the thicknesses of BOX(Buird OXide) layers and body bias on 65-nm and 28-nm processes by reducing the supply voltage. A Monte-Carlo based simulation is used in this work. The parasitic bipolar effect is suppressed by thicker BOX on FD-SOI structure.The simulation results are consistent with the alpha and neutron irra...