The drive towards a So@are-Defked which much of the processing is n A Warr, R J Wilkinson, J P McGeehan Centre for Communications Research University of Bristol, UK Radio (SDR) in Recent advances INTRODUCTION in analogue-to-digital conversion and controlled by digital processing technology have led to increasing reprogrammable digital hardware is placing new demands on the analogue RFji-ont-end...

We present a low-power Σ − ∆ modulator to be used in the baseband sections of wireless sensor network receivers with 0.65V Vdd operation. The design is optimized for low-power consumption and low operating supply by minimizing operational amplifier open-loop gain. Simple differential pair amplifiers with ≈ 40dB of open loop gain and low noise factor are employed as the integrator cores and guar...

Absrmcf--This paper describes a 10 bit 50MSampleIs CMOS DIA Converter fabricated in a lpm single-poly double-metal CMOS process. About 30Y0 power could be saved in video application by using a modified look-ahead circuit. The INL is less than 0.46LSB, and the DNL is less than 0.03LSB in the power-save mode. The settling time to 0.1% is less than 2013s. At 50MS/s the SFDR is 60dB. I b i s D/A co...

This paper discusses the design of a ripple-folding analog to digital (AID) converter in the current mode technique, which makes the design fully compatible with standard digital CMOS processes. The AID converter, which is designed in TSMC 0.35 Fm CMOS process, achieves 8 hits of resolution at a clock frequency of 100MHz. Simulated results show that the SFDR is better than 62 dB and the DNL and...

Abstract: A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18m CMOS. An opampsharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB (ENOB = 9.69 bits) and a peak SFDR of 76 dB, while maintaining more than...

– The theoretical analysis gives an overview of the functioning of DDS, especially with respect to noise and spurs. Different spur reduction techniques are studied in detail. Four ICs, which were the circuit implementations of the DDS, were designed. One programmable logic device implementation of the CORDIC based quadrature amplitude modulation (QAM) modulator was designed with a separate D/A ...

A 10b multibit-per-stage pipelined ADC incorporating merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are f0.40 LSB and f0.48 LSB, respectively. The ADC fabricated in a 0.25 pm CMOS occupies 3.6 mm2 active die area and consumes 208 mW under a 2....

This letter presents an accuracy enhancement technique utilized in 16 bit fully differential successive-approximation-register analog-to-digital converters (SAR ADC). For noise performance improvement to obtain a higher ENOB, the residue measurement which statistically estimates input residual error of comparator with Gaussian fitting is presented. The ADC digital output compensated by results....

This work describes a 6b 1.4GS/s 65nm CMOS DAC based on a current cell matrix with a 2-D INL bounded switching scheme. The proposed switching scheme reduces current matching errors in both row and column lines with a simple rowcolumn decoder. The proposed area-efficient deglitching circuit minimizes the timing error of each current cell and reduces the required number of transistors by 40% comp...