Reconfigurable systems can attain different configurations at different times thereby altering their functional abilities. Such systems are particularly suitable for specific classes of applications in which their ability to undergo changes easily can be exploited to fulfill new demands, allow for evolution, and improve survivability. This paper identifies the main factors that drive the need f...

Reconfigurable computing is a computer architecture which is intended to fill the gap between the hardware and the software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware. Most commonly and widely used high speed computing fabrics deployed in reconfigurable computing are field-programmable gate arrays (FPGAs). This pap...

A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the array simplifies the access of the processing elements for data manipulations. The DPSS allows automatic mapping of high level datapath structures onto the rDPA without manual interaction. Optimization techniques are sketc...

Primary requirements of wireless multimedia handheld computers are high-performance, flexibility, energy-efficiency and low costs. A compromise for these contradicting requirements can be found in a heterogeneous SoC. Besides conventional architectures such a SoC contains domain specific coarse grain reconfigurable processors and fine-grain reconfigurable entities. The MONTIUM is a prototype of...

Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this introduction to reconfigurable computing, we give an overview of the hardware archi...

ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffers from fixed hardware after design, while ASIPs and reconfigurable processors suffer from the lack of a pre-established instruction set, making it difficult to program. An intermediate solution, reconfigurable coprocessors systems (RCSs), contains dedicated hardware (coproc...

We consider randomized simulations of shared memory on a distributed memory machine (DMM) where the n processors and the n memory modules of the DMM are connected via a reconfigurable architecture. We first present a randomized simulation of a CRCW PRAM on a reconfigurable DMM having a complete reconfigurable interconnection. It guarantees delay O(log *n), with high probability. Next we study a...

Automating Layout of Reconfigurable Subsystems for Systems-on-a-Chip by Shawn A. Phillips Chair of the Supervisory Committee: Professor Scott Hauck Electrical Engineering As technology scales, engineers are presented with the ability to integrate many devices onto a single chip, creating entire systems-on-a-chip. When designing SOCs, a unique opportunity exists to add custom reconfigurable fabr...

In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor...