A hybrid radix-4/radix-8 architecture targeted for high bit, general purpose, digital multipliers is presented as a compromise between the high speed of a radix-4 multiplier architecture and the low power dissipation of a radix-8 multiplier architecture. In this hybrid radix4/radix-8 multiplier architecture, the performance bottleneck of a radix-8 multiplier, the generation of three times the m...

This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. As a case study, the radix-2 and radix-4 FFT algorithms have been implemented on FPGA hardware. The synthes...

Multiplication is a commonly used operation of Digital signal processing. The objective of a good multiplier is to provide a physically compact, high speed and a low power consuming chip. A low power multiplier using a dynamic range determination unit and a modified upper/lower left-to-right in the partial product summation is designed. The proposed multiplier is based on the modified booth alg...

The multiplier and multiplier-and-accumulator (MAC) are the essential elements of the digital signal processing. Multiplication involves two basic operations: the generation of partial products and their accumulation. Partial products can be reduced by using the Radix_4 modified Booth algorithm. The design of a binary signed-digit partial product generator, which expresses each normal binary op...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...

This paper presents a merged multiplyaccumulate (MAC) hardware that is based on the modified Booth algorithm. The carry-save method is used in the Booth encoder, the Booth multiplier, and the accumulator sections to guarantee the fastest possible. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Also, the proposed ...