| We present a new low-complexity bit-parallel canonical basis multiplier for the eld GF2 m generated by a n all-one-polynomial. The proposed canon-ical basis multiplier requires m 2 , 1 XOR gates and m 2 AND gates. We also extend this canonical basis multiplier to obtain a new bit-parallel normal basis multiplier.

The accuracy of the multiplication depends on the precision of the multiplier. The variable precision floating point multiplier will have more accuracy when compared with the fixed precision multiplier. In this paper a variable precision floating point multiplier is considered. An effective BIST test pattern generator for variable precision floating point multiplier is proposed. A BIST TPG cons...

The present paper is an attempt to: 1- Demonstrate how money is created (by the nature of the system), and to estimate the inflation resulting from monetary factors in both usurious and non-usurious systems. Operational aspects of Islamic and non-Islamic banking systems are compared. 2- Introduce a corrective term to be added to the multiplier of the supply of money, in order to prevent the und...

Now a day’s multiplication and modulus takes crucial role so we are combining multiplication and modulus. A Novel multi-modulus multiplier with different widths of modulus operations. In this paper we have radix4 multi-modulus multiplier with 4bit, 32bit, 64bit and radix8 multi-modulus multiplier with 4bit, 32bit, 64bit.radix4 and radix8 multi-modulus multiplier using Residue multiplication is ...

Galois field arithmetic is commonly used in Reed-Solomon encoding and decoding. This paper presents the design of a combined 16-bit binary and dual Galois field (GF) multiplier. This multiplier is capable of performing either a 16-bit two’s complement or unsigned multiplication, or two independent 8-bit GF(28) multiplications in SIMD fashion. The combined multiplier is designed by modifying a c...

In digital signal processors multipliers play a major role because, high multiplication process is carried out in hardware part in digital circuits. Array multiplier also requires less space for implementation in ICs and is an efficient way of multiplication in digital integrated circuits [3-4]. In this paper we have designed and analysed a four bit array multiplier using 45nm CMOS process. Arr...

AbstmctA bit-level pipelined 12 x 12-b two’s-complement multiplier with a 27-b accumulator has been designed and fabricated in a 1.0-pm p-well CMOS technology. A new “quasi N-P domino logic” structure has been adopted to increase the throughput rate, and special pipeline structures were used in the accumulator to reduce the total latency. The chip complexity is approximately 10 OOO transistors ...

Domain decomposition techniques provide a flexible tool for the numerical approximation of partial differential equations. Here, we consider mortar techniques for quadratic finite elements in 3D with different Lagrange multiplier spaces. In particular, we focus on Lagrange multiplier spaces which yield optimal discretization schemes and a locally supported basis for the associated constrained m...

in this paper we introduce the notions of uniformly quasi-primary ideals and uniformly classical quasi-primary submodules that generalize the concepts of uniformly primary ideals and uniformly classical primary submodules; respectively. several characterizations of classical quasi-primary and uniformly classical quasi-primary submodules are given. then we investigate for a ring $r$, when any fi...