With an exponential rise in logic density and performance, FPGAs are becoming essential components in various electronic systems. However, increased logic density and more importantly programmability of FPGAs cause increased power dissipation, which limits deployment of FPGAs in power constrained consumer electronic products such as mobile systems. Voltage scaling is a well-known tool to reduce...

In this paper, two high performance full adder circuits are proposed. We simulated these two full adder circuits using Cadence VIRTUOSO environment in 0.18 μm UMC CMOS technology and compared the Power dissipation, time delay, and power delay product (PDP) of the proposed circuits with other 10 transistor full adders. Simulation results show that for the supply voltage of 1.8V, these circuits a...

In this paper Modified Booth Multiplier (radix-4) implemented by various adder. Partial product generated by booth encoder is added by various adder techniques to compare the performance parameter of multiplier. Performance parameter like area, path delay, fan out, speed of multiplier. Multiplication is an important fundamental function in arithmetic logic operation. Since, multiplication domin...

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset (SEU) immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the pr...

This work scrutinizes the implementation and performance analysis of novel self-timed asynchronous logic. These templates are based on a delay-insensitive (DI) logic paradigm known as NULL Convention Logic (NCL) that supports RTZ protocol, includes clock-free operation, dual-rail encoding and monotonic transitions. Potential benefits include inherent robustness, low power, reduced noise ratio, ...

A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) b...

The continued quest for finding a low-power and high-performance hardware algorithm signed number multiplication led to designing simple novel radix-8 multiplier with 3-bit grouping partial product reduction performed using magnitudes of the multiplicand multiplier. pre-computation stage constitutes magnitude calculation non-trivial computations required generate products. A new strategy is dep...

In this paper a new area efficient, high-speed and ultra-low power 1-bit full adder cell is presented. The performance: power, time delay and power delay product (PDP) of the proposed adder cell has been analyzed in comparison with the four existent low-power, high-speed adders. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology and intensive simul...