Bang-Bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by formulating the time domain waveforms. As a re...

The paper proposes a way of implementing a phase locked loop (PLL) motor speed controller. The main emphasis is on the FPGA implementation of the digital PLL. The closed loop sensing element is an optical tachometer, which outputs an impulse train with a frequency proportional to the motor rotational speed. This impulse train will be synchronized by the PLL to a reference impulse train of a giv...

In grid connected applications the synchronization of output signals of the converters to be connected with grid parameters frequency and phase is of great importance. Different methods based on Fourier transforms, zero-crossing detection, Kalman filters, phase-locked loops (PLL) and others are used for this synchronization. This paper presents a new PLL for synchronization of the output curren...

Multi-view face detection in open environments is a challenging task, due to the wide variations in illumination, face appearances and occlusion. In this paper, a robust method for multi-view face detection in open environments, using a combination of Gabor features and neural networks, is presented. Firstly, the effect of changing the Gabor filter parameters (orientation, frequency, standard d...

This paper presents a new circuit for clock generation. A new phase frequency detector is designed in 130nm CMOS process technology. The phase locked loop is designed to meet the 10BaseKR wire line communication standards. All the circuits are designed in current mode logic for high speed operation. The designed circuit dissipates mW. The voltage controlled oscillator has phase noise of -182. 2...

The present study was designed to develop a simple, validated liquid chromatographic method for the analysis of azithromycin in bulk and pharmaceutical dosage forms using ultraviolet detector. The best stationary phase was determined as C18 column, 5 µm, 250 mm × 4.6 mm. Mobile phase was optimized to obtain a fast and selective separation of the drug. Flow rate was 1.5 mL/min, Wavelength was se...

The present study was designed to develop a simple, validated liquid chromatographic method for the analysis of azithromycin in bulk and pharmaceutical dosage forms using ultraviolet detector. The best stationary phase was determined as C18 column, 5 µm, 250 mm × 4.6 mm. Mobile phase was optimized to obtain a fast and selective separation of the drug. Flow rate was 1.5 mL/min, Wavelength was se...

the present study was designed to develop a simple, validated liquid chromatographic method for the analysis of azithromycin in bulk and pharmaceutical dosage forms using ultraviolet detector. the best stationary phase was determined as c18 column, 5 µm, 250 mm × 4.6 mm. mobile phase was optimized to obtain a fast and selective separation of the drug. flow rate was 1.5 ml/min, wavelength was se...

In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less th...

For asynchronous sampled systems such as Polarization Division Multiplexed Quadrature Phase Shift Keying, (PDM-QPSK), phase and frequency of the sampling clock is typically not synchronized to the data symbols. Therefore, timing adjustment, so called clock recovery and interpolation, must be performed in digital domain prior to signal demodulation in order to avoid cycle slips. For the first ti...