Power consumption has become a critical concern in today’s VLSI system design. The growing market for fast floating-point co-processors, digital signal processing chips, and graphics processor has created a demand for high speed, area-efficient multipliers. The Modified Booth Recoding method is widely used to generate the partial products for implementation of large parallel multipliers, which ...

Arithmetic and Logic Unit (ALU), core unit of a processor, when used for scientific computations, will spend more time in multiplications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reducing delay in the multiplier reduces the overall computation time. Wallace multipliers perform in parallel, resulting in high speed. It uses...

The JPEG 2000 image compression standard is designed for a broad range of data compression applications. The Discrete Wavelet Transformation (DWT) is central to the signal analysis and is important in JPEG 2000 and is quite susceptible to computer-induced errors. However, advancements in Field Programmable Gate Arrays (FPGAs) provide a new vital option for the efficient implementation of DSP al...

Modular arithmetic operations l ike inversion, multiplication and exponentiation are used in several cryptography applications. A special modulo set of forms {21,2,2+1}are preferred over the generic modulo due to the ease of hardware implementation of modulo arithmetic functions as well as systemlevel intermodulo operations, such as RNS-to-binary conversion and sign detections. Key sizes in the...

A new scheme for the implementation of programmable FIR digital filters with 100% operational efficiency is presented in this paper. The term 100% operational efficiency implies that no zero bits have to be inserted between successive in−put data words in order the filter input to be synchronized with the filter output. Both the input data and the filter out−put are in two’s complement LSB−firs...

Low power consumption and smaller area are the most important criteria for the fabrication of DSP systems. Optimizing speed and power of the multiplier is a major design issue. However, speed and power are usual constraints conflicting to each other, so that increasing speed results in larger areas. Parallel multipliers like Braun’s multiplier are preferred over serial multipliers as they consu...

New VLSI circuit architectures for addition and multiplication modulo 2 1 and 2 1 are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are improved ...