Understanding the SEU induced failure modes specific to the Virtex SRAM FPGA is needed to evaluate the applicability of various mitigation schemes since many mitigation approaches were originally intended for ASICs and may not be effective or efficient within FPGAs due to the unique failure modes and architectures found in SRAM-based FPGAs. Through this work, we have shown that SEUs in FPGAs’ p...

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...

We propose and demonstrate silicon photonic integrated circuits (PICs) for free-space spatial-division-multiplexing (SDM) optical transmission with multiplexed orbital angular momentum (OAM) states over a topological charge range of -2 to +2. The silicon PIC fabricated using a CMOS-compatible process exploits tunable-phase arrayed waveguides with vertical grating couplers to achieve space divis...

Quantum-dot Cellular Automata (QCA) as a nanoscale transistor-less device technology offers distinguishing advantages over the limitations of CMOS circuits. While more than 2 decades of design progress have been achieved with QCA, a comprehensive composition approach for the layout design in this technology is needed. In this study, the Priority-Phased Decomposition-Driven (PPDD) QCA logic desi...

We report the first demonstration of polarisation insensitive all-optical wavelength conversion (AOWC) for single wavelength channel 640 Gbit/s return-to-zero differential-phase-shift-keying (RZ-DPSK) signal and 1.28 Tbit/s polarisation multiplexed (Pol-Mux) RZ-DPSK signals using a 100-m polarisation-maintaining highly nonlinear fiber (PM-HNLF) in a polarisation diversity loop configuration. Th...

____________________________________________________________________________ Abstract The present ISR describes the encircled energy(EE) analysis of pinhole images made on the M10 WFC3 1R-MUX at the Goddard Space Flight Center (GSFC) Detector Characterization Lab (DCL) on 29 May 2001. Analysis shows that the pinhole image’s centroid is stable within a 1-pixel area and the 80% of the encircled e...

This paper develops the architecture of a digital PWM controller for application in multi-phase voltage regulation modules (VRM’s) with passive current sharing. In this context, passive current sharing and VRM transient response are analyzed. A scheme for sensing a combination of the VRM output voltage and output current with a single lowresolution windowed analog-to-digital converter (ADC) is ...

With the advancement of technology, data converters are widely used in modern communication and digital signal processing. ADCs are basic building blocks in many applications including storage systems, optical communication, radar communication, instrumentation and high-speed serial data links[1]. Different categories of ADC architectures are available based on their speed, resolution and power...

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...