With the increasing complexity of VLSI devices, more complex faults have appeared. Most of previous fault diagnosis methods considered a single defect assumption. However, for present technologies and chip sizes, defects have tendency to be clustered. So, we propose a multiple fault diagnosis method using a fault selection table. The proposed method can diagnose multiple defects based on a sing...

To guarantee the temporal correctness of a digital circuit a set of multiple path delay faults called primitive faults need to be tested. Primitive faults can contain one or more faulty paths. Existing techniques can identify and test primitive faults containing up to two or three paths. Identifying and testing primitive faults that consist of a larger number of paths is impractical for large d...

The main thrust of this research is the development of an artificial intelligence (AI) system to be used as an operators' aid in the diagnosis of faults in large-scale chemical process plants. The operator advisory system involves the integration of two fundamentally different AI techniques: expert systems and neural networks. A diagnostic strategy based on the hierarchical use of neural networ...

Unfaulting seismic images to correlate seismic reflectors across faults is helpful in seismic interpretation, and is useful for seismic horizon extraction. Methods for unfaulting typically assume that fault geometries need not change during unfaulting. However, for seismic images containing multiple faults and, especially, intersecting faults, this assumption often results in unnecessary distor...

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accuratel...

This paper presents a didactic simulator for stuck-at (sa) faults on logic circuits. The tool has a set of features that helps to understand the concepts of single and multiple stuck-at faults, being these faults testable or not, and how to generate test vectors in order to test the detectable fault subset. An interface was developed to allow the edition of a circuit, the injection of faults an...

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accuratel...

Machine Learning (ML) software, used to implement an ML algorithm, is widely used in many application domains such as financial, business, and engineering domains. Faults in ML software can cause substantial losses in these application domains. Thus, it is very critical to conduct effective testing of ML software to detect and eliminate its faults. However, testing ML software is difficult, esp...