A new broadband in-phase power divider based on multilayer technology is presented. A simple design procedure is developed for the proposed multilayer power divider. An S-band four-way multilayer power divider was designed and measured. The simulated results are compared with the measured data, and good agreement is reported. The measured 15 dB return loss bandwidth is demonstrated to be about ...

Abstract—A compact dual-band power divider for GSM/DCS applications is proposed in this letter. Novel planar artificial transmission lines are applied to miniaturize the power divider and achieve wideband response. The proposed dual-band power divider is about 37% of conventional one. The design principle, simulated and measured results are all discussed. The measured results show that good per...

The implementation of a programmable high speed divider for a CMOS Frequency Synthesizer, using 0.35 μm CMOS technology, is described. The Frequency Synthesizer is part of a RF transceiver to work in the 2.4 GHz ISM (Industrial, Scientific and Medicine) band. The programmable divider employs: a divide-by-32/33 dual-modulus prescaler composed by a divide-by-4/5 synchronous counter, using the Ext...

The objective of this project is to develop a Programmable Frequency divider design for multi GHz PLL System implementation on FPGA using VHDL (hardware description language). The frequency divider architecture features 6 parallel divider chains, each one of them implementing a single division ratio. The desired frequency division ratio is then selected using the four control bits of an output ...

This paper proposes an idea to modify the conventional Wilkinson power dividers to have physically spaced output ports. The well-known internal resistor of Wilkinson power divider is now connected to output ports by two additional transmission lines to create a triangular shape power divider. Several modified power dividers are designed at frequency of 1.0 GHz and one of them is fabricated and ...

In this paper we design of an adaptive Nero fuzzy system with mixed-signal inputs and digital outputs. In this paper analog advantages including low die area, high speed and simplicity are added to the digital advantages, such as programmability, robust against noise and distortions. a new programmable Fuzzifier circuit based on mixed-signal input, and min circuit for inference and Multiplier/D...

In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator...

A reflective type fiber optic angular displacement sensor has recently been developed, which consists of a light source, an optical isolator, a four-port single-mode fiber bidirectional coupler, and a light intensity detection system (two silicon photodetectors and ananalog divider). By using a normal He-Ne laser with &2% stability in light intensity, we have achieved an angle resolution of 10e...

The design and simulation of a 1.35 GHz fully integrated CMOS frequency synthesizer for a double band receiver is presented. The proposed synthesizer is based in a wide-band PLL topology with a high reference frequency. This approach allows obtaining low phase noise, fast switching time, a low divider ratio and a reduction in the total chip area. Besides, the use of a novel charge-pump circuit ...