Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Since static compaction of scan vectors invariably leads to higher power for scan testing, the conflicting goals of low-power scan testing and reduced test data volume appear to be irreconcilable. We tackle this problem by using test data compression to reduce both test data volume and sc...

Nowadays, at-speed scan based testing is used for testing the performance of the given circuit. In the case of At-speed scan based test, excessive capture power due to power risky pattern may cause significant current demand, resulting in the IRdrop problem .In proposed method, all power risky patterns are discarded and considering power safe patterns and refining them.WSA switching activity is...

We present a new low-power BIST (built-in-self-test) for sequential circuits. State correlation analysis is first performed on the flip-flop values in the relaxed, compacted sequence for the undetected faults to extract spatial correlations among the flip-flops. The extracted spatial correlation matrix not only provides additional metrics through which the scan order may be altered, but also al...

In genetic association studies a conventional test statistic is proportional to the correlation coefficient between the trait and the variant, with the result that it lacks power to detect association for low-frequency variants. Considering the link between the conventional association test statistics and the linkage disequilibrium measure r(2), we propose a test statistic analogous to the stan...

A Low Transition LFSR(LT-LFSR) designed by modifying Linear Feedback Shift Register is proposed to produce low power test vectors which are given to Circuit under Test (CUT) to reduce the power consumption by CUT. This technique of generating low power test patterns is performed by increasing the co-relativity between the consecutive vectors by reducing the number of bit flips between successiv...

This paper proposes a generic multi-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping (selectively load/unload) many long scan chain switching activities. Based on the two-dimensional scan shift control, we can achieve low test power with simple and small overhead structure. We can further extend the s...