Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, ...

This paper presents the design and implementation of a low power pipelined 32-bit RISC Processor. The various blocks include the Fetch, Decode, Execute and Memory Read / Write Back to implement 4 stage pipelining. In this paper, low power technique is proposed in front end process. Modified Harvard Architecture is used which has distinct program memory space and data memory space. Low power con...

This chapter covers device and circuit aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate ...

In this paper we propose an efficient approach to design high-speed digital filters with low power consumption which is based on power supply voltage scaling and exploiting the excess speed that may be obtained by using maximally fast recursive filter structures. We also discuss several techniques to increase and obtain the maximal sample rate for recursive structures based on frequency masking...

Present generation of electronic design scenario demands low power architectures. In earlier days, power was secondary as the field was premature and main concerns of design engineers were size, throughput and cost. However trade off exists between the metrics namely, size, throughput, cost and power according to the famous design metric competition theory of VLSI systems wherein improving one ...

Subthreshold source-coupled logic (STSCL) is a logic family that contains a constant bias current in each logic gate. Logic operation is based on the steering of this current towards one of two load resistors using subthreshold dierential pairs. STSCL was proposed for its low power consumption due to the small voltage signal swing, as well its suitability for congurable circuits. In this work, ...

Because of the rapid growth of portable electronics, high density integrated circuits with low energy consumption and low electromagnetic interference (EMI) at high speeds are needed. It is well known that dynamic power dissipation is directly related to the number of the signal transitions in the circuit. Functional signal transitions are desirable, where spurious transitions (or glitches), ca...

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This paper proposes a bus-segmentation method that efficiently reduces the switched capacitance on the bus. The power consumed by the bus can, therefore, be substantially reduced. The basic idea of bus segmentation is to partition the bus into several bus segments separated by pass transistors. Highly communicating devices are located to adjacent bus segments, thus, most data communication can ...

In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some drawbacks are introduced in term of power leakage and reliability. Moreover, the scaled technology...