A Platform-Based Approach to Low-Power Receiver Design

A cryocooler survey has been performed on data of 235 cryocoolers, with cooling powers below some tens of watts and operating between 4 and 120 K. The state-of-the-art is discussed and trends are investigated on cooling performance, mass and size, cost, lifetime and reliability. The data were compared with earlier surveys to explore historical trends. Improvements in cooling performance were ma...

This paper proposes new eecient low-power systolic ar-chitectures for Full Search-Block Matching (FS-BM) motion estimation. These architectures allow to eliminate unnecessary computations, reducing the power consumption while preserving the optimal solution and the throughput. The new and traditional systolic architectures for motion estimation are compared in what concerns the required hardwar...

Introduction: Scientists and mathematicians are increasingly realizing the computational benefits of using modern, multi-core architectures. In response to this, manufacturers of traditional desktop graphics-processing units (GPUs) have evolved their architectures to create desktop and server GPGPUs (General Purpose Graphics Processing Units). These GPGPUs are quickly becoming the platform of c...

Micromachined microsystems and Micro Electro Mechanical Systems (MEMS) have made possible the development of highly accurate and portable sensors and instrument for a variety of applications in the health care, industrial, consumer products, avionics, and defense. Design of low-power circuits for these applications, and use of micromachined sensors and actuators in combination with integrated c...

Flexibility and Portability has increased the requirement of Low Power components in fields like multimedia, signal processing and other computing applications. Adders are the essential computing elements in such applications. However the present adder architectures with hybrid/heterogeneous features provide performance variations but limits to consume less power. In this paper, low power heter...

A method to reduce the power dissipated by PLAs is presented in [3]. This method is addressing both static and dynamic PLAs. The objective is to minimize the number of literals and product terms of a logic function. However, [3] concluded that the static power dissipation of the NOR gates is the dominant power dissipation, and the optimization proposed cannot decrease significantly the power di...

Presented in this paper are low-power and high-speed algorithms and architectures for complex adaptive lters. These architectures have been derived via the application of algebraic and algorithm transformations. The strength reduction transformation is applied at the algorithmic level as opposed to the traditional application at the architectural level. This results in a power reduction by 21% ...