In this paper, we consider the use of a limited pipelining scheme in conjunction with a gate resizing technique to improve the optimal clock speed of a combinational logic block. Gate resizing is restricted to a small subset of the circuit, and target gates are identiied using a delay sensitivity metric introduced here. 1 Abstract In this paper, we consider the use of a limited pipelining schem...

in this paper a novel all-optical logic nand, nor and xor gate based on nonlinear directional coupler theory is demonstrated. we use the identical structure which contains three waveguides, for designing these gates; the only difference however, is the power of inputs light beam. in other words, while a beam with 4 w/μm in power considered as logical one, the output is nand gate and if a beam w...

Chaotic systems can yield a wide variety of patterns. Here we use this feature to generate all possible fundamental logic gate functions. This forms the basis of the design of a dynamical computing device, a chaogate, that can be rapidly morphed to become any desired logic gate. Here we review the basic concepts underlying this and present an extension of the formalism to include asymmetric log...

Abstract— Quantum dot Cellular Automata (QCA) is anticipated to allow for extremely dense nano-scale design and implementation of logic circuit over the Complementary Metal Oxide Semiconductor (CMOS). QCA has been considered as a promising alternative to CMOS technology for its lower power consumption, higher scale integration and higher switching frequency. Moreover, the basic element in QCA i...

| The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using diierent delay models such as unit delay, fanout delay, and random delay in power estimation of ...

| The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using di erent delay models such as unit delay, fanout delay, and random delay in power estimation of ...

Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. This paper proposes an improved design of a multiplier using reversible logic gates. Multipliers are very essential for the construction of various computational units of a quantum computer. The quantum cost of a reversible logic circui...

Integrated circuit design is entering an era of truly nanoscale transistors with minimum device geometries now at 32nm and soon to be at 25nm. While actual transistor and logic gate sizes are many times the minimum lengths possible, logic elements are becoming increasingly small and more closely packed together. There is now an increasing possibility of getting coupling errors where nearby logi...