Dynamic logic families offer good performance over traditional CMOS logic. This is due to the comparatively high noise margins coupled with the ease of implementation. The main drawbacks of dynamic logic circuits are lack of design automation, charge sharing, feedthrough, charge leakage, singleevent upsets, etc. But these draw backs can be eliminated using domino and NORA circuits but still lac...

Using computer-aided circuit simulation, the speed of RTD-based bistable circuits has been evaluated in terms of device parameters, such as the transistor’s fT and fmax, and circuit parameters, such as sizing. Two topologies studied in this work are: 1) monostable-to-bistable transition logic element (MOBILE), and 2) quantum bistable logic circuit (QBL). The transistors studied in this paper ar...

We study the problem of fault propagation, which is a very important and time consuming task performed by an ATPG tool, and develop a generic framework that supports generation of propagation functions per circuit line for both logic and timing faults. The proposed methodology is an alternative to the traditional function-based ATPG techniques for logic errors (such as stuck-at faults), but can...

-Built-in self-test (BIST) is a design technique that allows a circuit to test itself. It is a set of structured-test techniques for combinational and sequential logic, memories, multipliers and other embedded logic blocks. BIST consists of a controller, and circuits for input excitation and output validation. A BIST circuit comprises a scan monitor with hold logic and a signature generation el...

Reversible logic gates are very much in demand for the future computing technologies as they are known to produce zero power dissipation under ideal conditions. The applications of reversible logic gates include ultralow power, nano computing, quantum computing, low power CMOS design, optical information processing, bioinformatics etc. This paper proposes an improved design of a multiplier usin...

By introducing a parallel extension rule that is aware of independence of the introduced extension variables, a calculus for quantified propositional logic is obtained where heights of derivations correspond to heights of appropriate circuits. Adding an uninterpreted predicate on bit-strings (analog to an oracle in relativised complexity classes) this statement can be made precise in the sense ...

This module presents the basic structure of combinational logic circuits, and introduces the use of computer aided design (CAD) tools in modern circuit design. Combinational logic circuits use networks of logic gates to produce outputs that change in strict relation to input changes; that is, an output can only change state immediately after an input changes state. In a combinational circuit, s...

Logic Programming languages and combinational circuit synthesis tools share a common “combinatorial search over logic formulae” background. This paper attempts to reconnect the two fields with a fresh look at Prolog encodings for the combinatorial objects involved in circuit synthesis. While benefiting from Prolog’s fast unification algorithm and built-in backtracking mechanism, efficiency of o...

As the complexity of the modern VLSI design increases, logic rectification plays very important role for improving the speed and efficiency of design error correction. It is needed for both enabling efficient design revision and fixing implementation errors. This report introduces the general concept of logic rectification and compares the advantages and disadvantages of several different appro...

This paper presents a Variable Latency (VL) adder. It is introduced to work at a lower time delay than that required by a Ripple Carry Adder (RCA). It proposes a new technique called HOLD LOGIC. The VL-adder design is further modified to overcome the effects of negative bias temperature instability (NBTI). In the CLDC (Carry Length Detection Circuit), more number of components are used and it p...