FPGA based VLSI processor arrays provide an enormous computation performance along with the flexibility of reconfigurable logic. In the future, hybrid processors will become available that consist of a RISC core and configurable logic area on the same die. This allows for the efficient usage of a VLSI array as a coprocessor to the RISC core. Due to their high performance, VLSI array structures ...

Mobile and wireless devices suffer from technological limitations such as limited battery life and limited memory size. Hence, use of technologies for mobile applications is confined to those technologies that are faster and take small footprint in memory. Firstly, this paper presents a survey of technologies that can be used for realization of inference engine, satisfying the qualities mention...

This paper reports on the implementation of an Artificial Neural Network (ANN) on an Atmel AT6005 Field Programmable Gate Array (FPGA). The work was carried out as an experiment in mapping a bit-level, logically intensive application onto the specific logic resources of a fine-grained FPGA. By exploiting the reconfiguration capabilities of the Atmel FPGA, individual layers of the network are ti...

Ecient parallel schemes for carry-propagation-free addition of modi®ed signed-digit trinary numbers are presented. The necessary minterms for implementation using an optical programmable logic array area are derived. The proposed schemes require only a truth table of 25 entries compared with an earlier scheme of 625 entries. The proposed schemes are amenable to optical implementation. Experime...

This paper represents the combination of Reduced Instruction Set Computer (RISC) system using VHDL and implement. This paper presents a RISC processor designing to achieve various arithmetic operations. The RISC is a 20 bit processor. KeywordsArithmetic Logic(AL), Central Processing Unit(CPU), Control Unit(CU), Field Programmable Logic Array(FPGA), General Purpose Register(GPR), Program Counter...

B A C K F I R E ? In late June, Hong Kong media reported China’s PLA-AF (People’s Liberation Army – Air Force) would seek to become a ‘strategic air force’ with the acquisition of the Russian Backfire cited as a core tenet of this fundamental policy change. To best appreciate the potential strategic impact of the Backfire upon the Asia Pacific region it is worth exploring the capabilities of th...

Correct design of interface circuits is crucial for the development of System-onChips (SoC) using off-the-shelf IP cores. For correct operation, an interface circuit must meet strict synchronization timing constraints, and also respect sequencing constraints between events dictated by interfacing protocols and rational clock relations. In this paper, we propose a technique for automatically ana...

The theory of arrays is ubiquitous in the context of software and hardware verification and symbolic analysis. The basic array theory was introduced by McCarthy and allows to symbolically representing array updates. In this paper we present combinatory array logic, CAL, using a small, but powerful core of combinators, and reduce it to the theory of uninterpreted functions. CAL allows expressing...

Speedups from mapping four real-life DSP applications on an embedded system-on-chip that couples coarsegrained reconfigurable logic with an instruction-set processor are presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elements. A design flow for improving application’s performance is proposed. Critical software parts, called kernels, are accelerated on the...